Topic for #milkymist is now Radical Tech Coalition :: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs
<wpwrak> yup
<wpwrak> NOR is on 3.3 V. fpga core on the 1.x V (one or both, too lazy to look it up :)
<whitequark> I "like" how the isim happily eats incorrect syntax and produces undefined behavior
<whitequark> is this feature intended to taunt lazy engineers?..
<whitequark> also, simulating a reset edge concurrently with a clock edge is NOT a good idea.
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<whitequark> gah
<whitequark> I just made a processor with branch delay slot, which is at exactly PC(branch) + 3 position
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<lekernel> whitequark: your reset, like the rest, should be synchronous
<lekernel> they are many examples of designs with asynchronous resets (featuring strongly, of course, at the #1 community within broken IP-cores), but they do not map well to modern FPGAs and can cause metastability if you are not careful
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<GitHub115> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/ec4739401270bf0ad09360a0d00bbc29d250b3e3
<GitHub115> [migen/master] verilog: support for float parameters in instances - Sebastien Bourdeauducq
<GitHub193> [milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/ZPjt9Q
<GitHub193> [milkymist-ng/master] clkfx module - Sebastien Bourdeauducq
<GitHub193> [milkymist-ng/master] Multiply system clock - Sebastien Bourdeauducq
<GitHub36> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/6f8a6db40a64df0272daf25979d8dbe6fa984ce8
<GitHub36> [migen/master] verilog: get the simulator to run the combinatorial process at the beginning - Sebastien Bourdeauducq
<GitHub18> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/d6Iw2A
<GitHub18> [milkymist-ng/master] norflash tb: use get_fragment - Sebastien Bourdeauducq
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<GitHub170> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/xlCq0w
<GitHub170> [milkymist-ng/master] 32-device, 8-bit CSR bus - Sebastien Bourdeauducq
<GitHub166> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/1a845d45539662a78347f765cc6aa986ad728745
<GitHub166> [migen/master] 32-device, 8-bit CSR bus - Sebastien Bourdeauducq
<whitequark> lekernel: I meant the simulation
<whitequark> i.e. always #20 clk <= ~clk; initial reset = 1; #20; reset = 0;
<wpwrak> wolfspraul: first round of NOR torture: if the bug was still there, it would have caused a corruption with a probability of 99.92%. but no corruption was evident.
<wpwrak> wolfspraul: one more day of testing will add an extra safety margin of a factor of about 1000
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<krispaul> csr_addr = 5 finally :)
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<GitHub4> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/d21e095397ebbe45757cbaf06385878f3670062d
<GitHub4> [migen/master] fhdl: fix series of if/elif/else - Sebastien Bourdeauducq
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<GitHub156> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/135a2eb86899149d9877202600877577a6445983
<GitHub156> [migen/master] bank: support raw registers - Sebastien Bourdeauducq
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<GitHub156> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/KMYTBw
<GitHub156> [milkymist-ng/master] uart: new design using FHDL and bank (TX only, incomplete) - Sebastien Bourdeauducq
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