lekernel changed the topic of #milkymist to: Mixxeo, Migen, Milkymist-ng & other Milkymist projects :: Logs: http://en.qi-hardware.com/mmlogs :: Mixxeo preorder lists.milkymist.org/pipermail/devel-milkymist.org/2013-May/003344.html
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<lekernel> hi _florent_
<lekernel> I saw your problems with the IDDR clock frequency limit
<_florent_> hi
<lekernel> when you are using DDR mode, is it reasonably possible to use local clock inversion, or does this result in Xilinx-traditional massive skew and jitter?
<_florent_> I don't know yet since for now I'm using SDR mode
<_florent_> but with SDR mode I'm limited to 625 MHz
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<_florent_> the phy is now working at 600MHz
<lekernel> if they did it right, but I'm not sure they did, using DDR mode should be as simple as setting the DDR parameter and having CLK0=clk, CLK1=~clk
<_florent_> I've implemented the read & write leveling
<lekernel> hm, are you using DQS for reading?
<_florent_> I've tried that, but it was not working ;)
<lekernel> ok, sounds like slowtan6 then
<lekernel> what happened?
<_florent_> don't know exactly, I haven't simulated it, just that it was not working on board, I plan to simulate it
<lekernel> but the P&R didn't complain about unroutable clocks or such?
<_florent_> IIRC it was able to route
<lekernel> and then? what happened to the data?
<_florent_> for the read leveling, I'm only using the bitslip + idelay, and I calibrate the bitslip + idelay by sampling the read pattern of the ddr
<_florent_> don't remember for the DDR mode, it was really a quick test
<lekernel> that's not good, the DDR3 read timing with respect to the clock can vary by more than one bit time over PVT
<lekernel> you can do that with DDR, but with DDR2 the timing margin is very small, and it's negative with DDR3
<_florent_> I don't plan to run the phy at more than it is running now (DDR600)
<lekernel> I wonder if some chips have random clk-data jitter that would make this always fail no matter the bitslip/idelay settings...
<lekernel> well it can work at 600Mbps/pin
<lekernel> but DDR3 is spec'd to 1600 :)
<lekernel> then you need to use DQS
<_florent_> but if you have a little time to explain your solution with a schematic, I can try to implement it
<lekernel> of course, thanks to the slowness of kintex, you'd only reach 1300 or so
<lekernel> or try to overclock
<lekernel> I'll try to post some document to the list...
<_florent_> ok thanks
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<juliusb> lekernel: did you get any further with your evaluation of the Tabula tools?
<lekernel> not really, their software won't compile any design due to bugs with subprocess management and lockfiles
<juliusb> !!
<lekernel> yeah, welcome to EDA-land
<juliusb> you get what you pay for ;)
<juliusb> but it really fails to do even an adder or something?
<lekernel> didn't they raise $108M in venture capital lately?
<lekernel> the HDL compiler won't even begin to read the source, it crashes before
<larsc> we should try to do that too (raise a couple of millions of vc)
<juliusb> 108mil don't go far when you make chips
<larsc> lekernel: you do your con man trick and the money will flow in
<lekernel> phew
<lekernel> it's overrated
<lekernel> even academia can make chips
<larsc> juliusb: but it's sufficient for one or two parties ;)
<lekernel> or bitcoin miners
<juliusb> the things academia make are not intended to compete in a market place, and so are many nodes behind cutting edge
<juliusb> also not intended for mass production
<wpwrak> larsc: that's the first viable plan for actually making money with the things we do ! :)
<Fallenou> make a lot of parties, they will need a lot of VJ equipments
<Fallenou> that's where we kick in
<lekernel> haha
<lekernel> I could try actually
<wpwrak> the kickstarter party project :)
<larsc> ah tabula is that TDM FPGA company
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<lekernel> actually, due to some improbable incident I'm invited to one of those "high level" meetings next week that rejon would love. it is, of course, a BS-heavy environment and I'm not quite sure what to say there as I'm not working with the internet of things, the technological singularity, etc.
<wpwrak> visit the nearest buzzword generator, collect and remember a few pompous expressions, and you'll be fine
<lekernel> maybe I'd rather stay home and code or start to reverse engineer that turbomolecular pump I got from the trash a couple days ago
<wpwrak> when people don't understand, they're often afraid to ask
<wpwrak> think of the buffet ! :)
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<larsc> to paraphrase edison: We often miss opportunities because they are dressed in suits and look like boring social events ;)
<wpwrak> the philosophical revenge of the working class ;-)
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<GitHub88> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/odocnA
<GitHub88> migen/master 932bfa7 Sebastien Bourdeauducq: bus: Wishbone -> LASMI bridge (untested)
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<GitHub115> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/SDYiDg
<GitHub115> migen/master 3a284b9 Sebastien Bourdeauducq: actorlib: LASMI DMA (untested)
<GitHub119> [migen] sbourdeauducq pushed 2 new commits to master: http://git.io/fU1ArQ
<GitHub119> migen/master aea3b59 Sebastien Bourdeauducq: genlib/fsm: fix handling of zero delayed_enter
<GitHub119> migen/master fe54c68 Sebastien Bourdeauducq: lasmi: fix minor problems
<larsc> what does the L stand for btw?
<lekernel> lightweight
<larsc> what does it make lightweight
<wpwrak> the heavy thrusters ? ;-)
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