lekernel changed the topic of #milkymist to: Mixxeo, Migen, Milkymist-ng & other Milkymist projects :: Logs:
http://en.qi-hardware.com/mmlogs :: Mixxeo preorder lists.milkymist.org/pipermail/devel-milkymist.org/2013-May/003344.html
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GitHub1>
milkymist-ng/asmi d557a9a Sebastien Bourdeauducq: asmicon/bankmachine: fix full selector
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GitHub1>
milkymist-ng/asmi 3917ab4 Sebastien Bourdeauducq: videomixer: rescale pots
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GitHub189>
migen/master 0c52c08 Sebastien Bourdeauducq: bus/asmibus: fix slot aging timer
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GitHub182>
migen/master ac2cde0 Sebastien Bourdeauducq: asmibus: remove port sharing
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GitHub169>
milkymist-ng/asmi 279a145 Sebastien Bourdeauducq: videomixer: add fb.c
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GitHub169>
milkymist-ng/asmi b2319fd Sebastien Bourdeauducq: videomixer: support different resolutions
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lekernel>
new slowtan6 bug: 800x600 on both channels fucks up all PLLs, including the system clock one
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kristianpaul>
urgh
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kristianpaul>
how come?
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lekernel>
because no spartan6 feature works correctly, ever
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wpwrak>
makes you wonder how the others fpgas are ...
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lekernel>
I had hopes for Tabula, but it turns out their software crashes way before reading the first byte of a HDL source file
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wpwrak>
do you think the spartan thing is just a synthesis problem, or hardware ?
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lekernel>
it could be because I'm not using the GCLK pins to drive the PLLs...
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lekernel>
but it looks hardware. works fine until a certain pixel clock frequency, then everything breaks down (including serial output)
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lekernel>
also works if only one channel is active
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wpwrak>
hmm. could it be power ?
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lekernel>
for some reason it doesn't happen in bios
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lekernel>
the PLLs lock and everything looks normal there
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kristianpaul>
perhaps you dont wanna do it the xilinx way (hardware thing) ?
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kristianpaul>
how are you driving the PLLs instead? ahh you using exp connector ;) isnt?
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kristianpaul>
that could explain part of it,
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kristianpaul>
why not use glck from memcard?
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kristianpaul>
just to give it a chance
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kristianpaul>
play safe :)
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GitHub175>
milkymist-ng/asmi cd910b8 Sebastien Bourdeauducq: videomixer: timeout on IDELAY busy
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GitHub178>
milkymist-ng/master 81d35ef Sebastien Bourdeauducq: videomixer: add fb.c
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GitHub178>
milkymist-ng/master 13bf6f5 Sebastien Bourdeauducq: videomixer: timeout on IDELAY busy
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GitHub178>
milkymist-ng/master bb43171 Sebastien Bourdeauducq: videomixer: support different resolutions
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davidc__>
lekernel: the PLLs are sourced from logic lines?
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lekernel>
davidc__, it goes through the general interconnect
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davidc__>
Ah, yeah, Xilinx FPGAs really don't like when you do that
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davidc__>
lekernel: if you can; try hand-wiring a *CLK capable input to the clock signal
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davidc__>
and see if that fixes it
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lekernel>
I don't really understand why they don't like this
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lekernel>
is it because of jitter? internal crosstalk?
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lekernel>
duty cycle distortion?
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davidc__>
lekernel: Probably a combination of all of the above + black voodoo magic
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lekernel>
I don't believe in black voodoo magic :)
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davidc__>
lekernel: the occasional sacrifice is needed to get timing closure
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lekernel>
swearing seems to work too
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lekernel>
at least mine does
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lekernel>
this is kinda frustrating, the picture with only 1 channel really looks clean in 800x600 now ...
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lekernel>
maybe I should just wait for the mixxeo boards
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GitHub29>
milkymist-ng/asmi 3240413 Sebastien Bourdeauducq: top: better performance
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