<lekernel>
whitequark, I'd suggest you use Migen for the RTL to netlist step
<lekernel>
the AST is much simpler than Verilog's
<lekernel>
there's some very draft code here https://github.com/nakengelhardt/mist and EDIF output for designs made entirely of instances is in Migen (and you can feed it to the Xilinx P&R)
<lekernel>
and you can, of course, run the Migen Verilog back-end to get Verilog netlists for free (nice for debugging)
<GitHub91>
NetBSD/master 05cdb65 Yann Sionneau: First kernel to be able to print messages to UART console on Milkymist SoC
<ysionneau>
ohoh, if whitequark starts to work on fpga tool ... then we might get something working nice in a short time :)
<ysionneau>
good to know you are interested in fpga tools
<whitequark>
heh
* whitequark
is reading lekernel's pdf
<whitequark>
ok, I see
<whitequark>
it's very convenient that the process consists of self-contained stages
<whitequark>
so I could e.g. take netlists in EDIF and output bitstream while using someone else's synthesis tools (say migen).
<whitequark>
what would be a good (xilinx, I assume) fpga series, for which most bitstream details are known?
<ysionneau>
it seems most of wolfgang work has been done on small Spartan 6 fpgas
<lekernel>
yes, afaik xilinx bitstreams are better known than altera's
<ysionneau>
and he understood a big deal of the bitstream format, since he was able to generate working bitstreams with his tool
<lekernel>
some of the ISE interfacing work is already done with migen, you just have to add mode="mist" to the build function call to use the - currently extremely limited - synthesis support
<whitequark>
judging by his Makefiles he used x6slx9
<lekernel>
would make it a tad easier to use your work if we have the same board :)
<whitequark>
papilio pro it is, then
<wpwrak>
a bit over-engineered (you don't need ram and i think you could load the bitstream over jtag as well). but it would probably be hard to find something simpler
<whitequark>
wpwrak: which one?
<ysionneau>
xiangfu was doing a very simple s6 board IIRC
<ysionneau>
but you have to do it yourself
<lekernel>
RAM is great :) you want a netbsd with 1080p framebuffer demo, right?
<ysionneau>
you cannot buy it
<wpwrak>
both actually :)
<wpwrak>
lekernel: heh ;-)
<wpwrak>
ysionneau: you could fab and sell them ;-)
<whitequark>
ysionneau: I'd prefer to have as few points of failure as possible :)
<ysionneau>
whitequark: I understand
<whitequark>
so, bitstream (binary) corresponds 1:1 to a floorplan (textual)?
<whitequark>
in fpgatools
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<ysionneau>
AFAIK yes
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