lekernel changed the topic of #milkymist to: Mixxeo, Migen, MiSoC & other Milkymist projects :: Logs: http://en.qi-hardware.com/mmlogs
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<ysionneau> barmstrong: you can still publish in your blog which Migen SHA-1 you are using :)
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<lekernel> rjo, hi
<lekernel> any ideas for better name for the size module? fiter/fslice/freversed are not that related to sizes ...
<lekernel> *for a better name
<lekernel> rjo, what is #Subsignal("iob"
<lekernel> in lx9_microboard?
<lekernel> rjo, vga(_out) should use the same signal names as in https://github.com/m-labs/migen/blob/master/mibuild/platforms/mixxeo.py#L69
<rjo> lekernel: "container" since these imeplement analogous functions to what python calls "emulating container types".
<rjo> lekernel: or "bits.py" ?
<lekernel> bitcontainer? :)
<rjo> lekernel: sounds good
<lekernel> can you send a rename patch? I have merged yours already
<rjo> lekernel: will do.
<rjo> lekernel: ah. that iob should not be commented out.
<rjo> lekernel: in general, i think it is approriate to offer different "views" onto the same pins in a platform (like pmod and pmod_diff in lx9 microboard). do you agree?
<rjo> lekernel: where is vga(_out)?
<lekernel> also, I'm thinking about phasing out the period parameter in CRG_ as using lookup_request and adding platform commands in do_finalize (which was added later) is more powerful (also works with user CRGs)
<lekernel> yes, having pmod + pmod_diff with the same pins sounds good
<lekernel> but right now there's pmod0/pmod1 with pins (respectively)
<lekernel> F15 F16 C17 C18 F14 G14 D17 D18
<lekernel> H12 G13 E16 E18 K12 K13 F17 F18
<lekernel> and the pmod_diff has pins
<lekernel> F15 C17 F14 D17 H12 E16 K12 F17
<lekernel> F16 C18 G14 D18 G13 E18 K13 F18
<lekernel> why is the order mixed like that?
<rjo> lekernel: good. also the try: except Constraint things should be refactored to look more like: if plat.is_allocated(..): platform.add_...()
<rjo> lekernel: request pmod_diff if you want differential pins io and iob. pmod0 or pmod1 if you want the connectors dingle-ended.
<rjo> single
<lekernel> yes, but the pin order wildly differs. I would have expected pmod0 to be "F15 C17 F14 D17 H12 E16 K12 F17" (positive pins) and pmod1 "F16 C18 G14 D18 G13 E18 K13 F18". there's probably a reason for it, but it just looks strange atm.
<lekernel> the python coding style is usually inclined towards trying doing things and then catching exceptions, instead of testing if the operation will work
<lekernel> vga is in zedboard
<rjo> lekernel: pmod0/1 is according to connector numbering. pmod_diff is according to differential signals on the fpga. afaik the pairing is fixed. isn't it?
<lekernel> ah, yes, I see
<rjo> lekernel: true. but i still think there could be a more readable way to do it...
<rjo> lekernel: i'll send patches for the iob lx9, the bitcontainer and the vga. anything else?
<lekernel> add period constraints instead of using the "period" argument of CRG_*
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<rjo> lekernel: sent patches to list
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<rjo> lekernel: a few thousand bytes to large. i guess you get moderator email. i didnt do rename recognition in format-patch...
<lekernel> yes, accepted it onto the list
<lekernel> committed, thanks
<rjo> lekernel: just noticed that i somehow messed up the authorship of that one patch...
<lekernel> hmm, yes
<lekernel> do you want me to try and fix it? it's a small patch...
<lekernel> (and such fixes are messy afaik)
<rjo> lekernel: i don't care.
<lekernel> ok
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