lekernel changed the topic of #milkymist to: Mixxeo, Migen, MiSoC & other Milkymist projects :: Logs: http://en.qi-hardware.com/mmlogs
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<ysionneau> very pretty!
<ysionneau> what software has been used to make this picture?
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<lekernel> hmm, don't remember atm (the design guys did it)
<lekernel> I just remember it renders amazingly fast for a ray tracer, less than a minute
<wpwrak> very elegant design
<ysionneau> yep
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<davidc__> lekernel: what are the flash A / flash B buttons for? boot image selection?
<davidc__> or for FX triggers?
<lekernel> FX triggers. it's not *that* nerdy :)
<kristian1aul> pretty and fresh indeed
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<barmstrong> that looks awesome. very polished!
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<rjo> lekernel: did you have a chance to look at the patches i sent? https://github.com/jordens/migen/compare/for-upstream
<larsc> I demand a refund: http://metafoo.de/mixxeo.jpg ;)
<ysionneau> ahah
<ysionneau> this one is trying to escape
<lekernel> rjo, got them, will check them out shortly. been very busy with other things lately.
<lekernel> larsc, how does it stick? from the solder flux?
<lekernel> larsc, did you fix the power problem by the way?
<larsc> didn't try yet
<larsc> I think the resistor is soldered to one of the pads
<larsc> just with the wrong end
<larsc> and the power issue is a bit strange anyway, sometimes it works just fine
<lekernel> ah, so it's actually missing from the R16 pads?
<larsc> yes
<lekernel> I see. will send that pic to creotech.
<rjo> lekernel: thanks.
<lekernel> larsc, is the power problem also happening on other computers?
<lekernel> or with a hub? have you checked the power with a scope and see if there's a drop?
<larsc> I only tried shortly on two different laptops and what I was seeing is that the board would randomly reset itself during boot
<larsc> I'm only assuming that it is a power issue
<larsc> I'll try to actually get the board up and running next week
<larsc> got too much stuff at work that still needs to be done before I go on vacation and I don't want to distract myself for now
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<lekernel> rjo, looking at the signed bug atm; seems the transfer of negative numbers between iverilog and python is buggy
<lekernel> a = Signal((3, True), reset=-4) ==> s.rd(a) returns -4
<lekernel> a = Signal((4, True), reset=-4) ==> s.rd(a) returns 4
<davidc__> lekernel: there's a bug in value_bits_sign FWIW (* operator doesn't return a (bits, sign) tuple - just bits)
<davidc__> lekernel: I think I have a patch, but I'm not 100% on whether I have the sign flag right for all cases :)
<lekernel> all cases? result is signed if any operand is signed
<davidc__> yeah, I had False, True, True; just wanted to make sure I understood exactly what value_bits_sign was returning
<lekernel> problem is in verilog or iverilog
<lekernel> xilinx fuse also prints 4
<lekernel> I wonder wtf the verilog standard came up with again this time ...
<lekernel> http://pastebin.com/5395ZhyR gives the expected -4; so sign extension works - but they made an exception for constants?!
<lekernel> ah, got it
<lekernel> the "-X'sdY" syntax sets bit X in value Y, which may or may not be the sign bit
<lekernel> sign extension with constants otherwise works. this is again an imbecilic thing to do, but at least it won't be hard to fix.
<lekernel> will do that tomorrow. gn8.
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