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<alyssa>
bbrezillon: That seems very reasonable, although I don't quite understand the motivation for seqnums
<alyssa>
Wouldn't it be just as easy to have the cache and seqnums combined?
<alyssa>
So then valid? is checking if shader_meta != NULL, and invalidate is just `shader_meta[..] = NULL`?
<alyssa>
Or 0, I guess.
<bbrezillon>
alyssa: cache is per-batch, and iterating over all batches to invalidate is not that great if you have a lot of them sticking around
<bbrezillon>
and if you just have a dirty flag at the ctx level, and batch are being swapped, you lose the dirty information as soon as one batch updates its descriptor
<bbrezillon>
the advantage of seqnums is that invalidation is just as fast as dirty checks
<bbrezillon>
the drawback is the extra u64 per desc type, but given how many fields we already have attached to the batch/context objs, I'm not sure it makes a huge difference
<alyssa>
bbrezillon: Ahhhh, I didn't see that one was per-ctx and the per-batch
<alyssa>
In an "ideal" world (one where commits were free and instant :p), we'd have a fixed maximum # of batches (32 or 64), and then this would all just become bitmasks on the ctx (in essense, vec64 with 1-bit ints :P)
<alyssa>
AFAIU freedreno has a system like that
<alyssa>
but this is totally orthogonal from the current work, so given the constraints of iterated improvement, +1 ack on the seqnum approach
<bbrezillon>
alyssa: we should probably make sure caching actually helps improving the perf before merging that
<bbrezillon>
for shader_meta, I checked that there were cache hits, but I didn't check the hit rate
<alyssa>
bbrezillon: ack.
<alyssa>
(fwiw, the index cache was getting like 98% hit rate on some workloads)
* alyssa
isn't sure how real apps use GL so..
<alyssa>
I know in some circles there's a mantra "state changes are slow", so apps bend over backwards to batch things on their end
<alyssa>
On modern hw I don't... really think state changes are that much of an issue, certainly not on midgard which is descriptor based anyway. but we can cash in on that caching
<bbrezillon>
caches at everylayer
<alyssa>
(cache in?)
<bbrezillon>
and then we wonder why our apps take so much memory
<bbrezillon>
:)
<alyssa>
:D
<bbrezillon>
alyssa: BTW, how do you test compute changes?
<bbrezillon>
(I mean, changes to pan_compute.c)
<bbrezillon>
this part of the rework is completly untested :-/
<alyssa>
deqp-gles31
<alyssa>
with the appropriate MESA_DEBUG=deqp and GLES_VERSION_OVERRIDE=3.1
<alyssa>
any test ending matching *compute or compute.* is a good candidate
<alyssa>
won't all pass of course but most should, we should probably get CI eventually but we're too far off still
<alyssa>
OK -- driver location
<alyssa>
Er that's an issue with offline compilation isn't it.
<alyssa>
I guess deferring to a bit
<alyssa>
okay, have fragment out generating IR
<alyssa>
so now passthrough fragment shaders have IR generated. which is... something?
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<alyssa>
have IR for the five different ld/st ops needed for basic shaders
* alyssa
class, but after that - onto ALU!
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<chewitt>
HdkR: there is mainline kernel support for VIM3L (G31) and u-boot support is merged/queued for 2020.04
<chewitt>
(reading backlog)
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<HdkR>
chewitt: Neato
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<maccraft123>
how's performance of panfrost on rk3288?
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<HdkR>
About what you'd expect from an 81GFLOP GPU
<HdkR>
Or 68GFLOP depending on how you do the maths
<maccraft123>
HdkR: is it comparable to gm45 integrated graphics?
<HdkR>
That was old GMA 4500 or something? I don't recall its performance level
<maccraft123>
barely runs minecraft on lowest settings
<maccraft123>
HdkR: gma4500mhd
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<tlwoerner>
alyssa: working on panfrost for T620 (i.e. odroid xu3/4) => we could list that as a potential GSoC project? ;-)
<anarsoul|2>
that could be a bit hard for GSoC
<alyssa>
tlwoerner: mayhaps, but anarsoul|2 is right
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