<narmstrong>
AFBC_FORMAT_MOD_SPLIT, AFBC_FORMAT_MOD_SPARSE, AFBC_FORMAT_MOD_TILED are the main layout options
<icecream95>
I've only been looking at single 16x16 superblocks at a time, so I haven't investigated how the superblocks are laid out yet.
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<alyssa>
You mean there is more than one format?
<alyssa>
*sigh*
<alyssa>
tomeu: I mean I've been working on purely compiler fixes but should be orthogonal to your stuff
<tomeu>
alyssa: ok, I thought you would be hacking on the sampling operations in parallel, so we can test our stuff with kmscube or glmark2
<tomeu>
give me an hour max to finish my emission code, then you can test it all yourself when you get to the compiler
<alyssa>
tomeu: Sure :)
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<alyssa>
OK, constant rule I see:
<alyssa>
Suppose there is a single 60-bit constant (but not a second).
<alyssa>
If the top 4-bits are < 8, copy them to the top 4-bits of the second 60-bit constant.
<alyssa>
If they are not, the second 60-bit constant remains zero.
<alyssa>
What happens with two such constants is TBD.
<tomeu>
alyssa: hmm, unsure of how we want to submit to the hw the texture descriptors in pre-allocated BOs, as the postfix has a pointer to an array of descriptors on bifrost
<alyssa>
tomeu: Hmm?
<alyssa>
Oh.
<tomeu>
on midgard, we have an array of pointers, so we can put pointers to our descriptors in the trampoline array
<tomeu>
but not on bifrost :/
<alyssa>
Right, right, yeah
<alyssa>
Not a problem!
<alyssa>
Prepack it and put the packed one in CPU (cached) memory in the CSO
<alyssa>
so the draw-time overhead is just a very tiny memcpy, with zeor packing logic needed
<alyssa>
(On midgard, we have essentially an 8-byte memcpy overhead for the pointers.)
<alyssa>
If you want f a n c y, you can do tricks to track when textures get rebound and minimize even that (what bbrezillon had worked on a bit). But diminishing returns at some point
<cwabbott>
alyssa: that sounds like a different workaround for the for the upper 4 bits ordering thing
<tomeu>
yeah, I for some reason remembered that the pointers to the texture descriptors are stable across draws, but just checked and they are allocating those along the other descriptors in the draw
<cwabbott>
iirc the compiler that I was looking at just swapped them
<tomeu>
alyssa: I think that, as long as the memcpy implementation is sane for uncached memory, the overhead shouldnt' be that big
<alyssa>
cwabbott: Indeed. But (from G52 blob and G31 hardware) -- if I don't do any workaround, it INSTR_INVALID_ENC's. If I swap according to either of your rules, it reads back random data.