10:00 <cwabbott> well, the point of pre-RA scheduling is precisely to get things in the "optimal-ish" order *before* adding false dependencies

10:00 <cwabbott> so the post-RA scheduler forming clauses can still do whatever the pre-RA did, because that would be a no-op

10:01 <cwabbott> the advantage of post-RA is that it can be even more aggressive (no need to worry about register pressure) and it can schedule live-range splits better

10:02 <cwabbott> i think that as soon as you have any kind of live-range splitting (spilling or moving) then you kinda want a post-RA scheduler forming clauses

10:02 <amonakov> was there something wrong about my questions yesterday? surprised they were ignored

10:03 <cwabbott> you *can* do post-RA scheduling and take advantage of the additional temp registers (cf lima gp) but it's really difficult

10:06 <cwabbott> amonakov: sorry, there are either 2 or 3 temp registers per instruction: instructions are grouped into pairs (FMA and then ADD) and then pairs are grouped into clauses (up to 8 per clause), and each instruction in each pair can read the result of the previous pair within the same clause through T registers, and ADD can read the result of FMA in the same pair through another T register

10:07 <cwabbott> OoO scheduling just means reordering instructions for register pressure/latency/etc

10:07 <amonakov> how is it different from just "scheduling"?

10:07 <cwabbott> it's the same thing

10:08 <cwabbott> i think alyssa had a "scheduler" that just put things into clauses without reordering but it's not the "normal" usage of the term

10:08 <cwabbott> not sure if it does reordering by now

10:10 <amonakov> I think in GCC we know "pack into clauses" functionality as "bundling" (at least for Itanium, probably other VLIWs too)

10:10 <amonakov> thank you

10:16 <robmur01> yeah, to first approximations, what Bifrost calls "clauses", IA-64 calls "bundles"

10:19 <robmur01> (although maybe bundles are closer to tuples... my approximations are very very approximate)

10:22 <amonakov> I think a term like "out-of-order scheduling" should be reserved for more rare stuff where instruction appear out of logical order (due to delay slots or "deferred" register writes within a bundle/clause)

14:01 <alyssa> cwabbott: TBF I do have patches to do OoO scheduling with the current "scheduler" but yes "bundler" is more accurate.

14:03 <alyssa> cwabbott: so if I do clause forming post-RA (out of order but constrained by false deps), do I even need a custom pre-sched pass or could I just drop nir_opt_scheduler in?

14:03 <alyssa> I wasn't impressed by nir_opt_schedule when I last looked but maybe I was using it wrong.

14:05 <alyssa> amonakov: "reserved for more rare stuff where instruction appear out of logical order" we do this for Midgard, and will soon do this for Bifrost

14:08 <amonakov> (ab)using delayed register writes?

14:09 <cwabbott> alyssa: in theory you could use nir_opt_scheduler, but yeah rolling your own might be better

14:09 <cwabbott> for bifrost it's kinda simpler, because you don't really need to worry about latency at all except for memory latency

14:10 <alyssa> "you *can* do post-RA scheduling and take advantage of the additional temp registers (cf lima gp) but it's really difficult" still seems like a sticking point

14:11 <cwabbott> well, if you're not willing to give up the additional temp registers then you're kinda stuck in between a rock and a hard place

14:12 <cwabbott> in order to do "proper" pressure-limited coalescing you need the ability to insert moves during RA, no matter what RA algorithm you use

14:12 <cwabbott> and not to mention spilling

14:13 <cwabbott> i guess you could do SSA-based RA by treating each clause as like a giant instruction with multiple definitions and whatnot

14:14 <alyssa> F'naaaaaaaaa

14:14 <cwabbott> maybe if you really want to use the temp registers, and want to deal with the pain of inserting live-range splits into clauses after the fact, that might be the way to go

14:17 <amonakov> at that point, isn't it easier to implement an integrated RA+scheduler? general-purpose RAs are complicated by dealing with register classes and what not, on GPUs its way more regular

14:18 <alyssa> Hahahaahahahahaha

14:19 <alyssa> sorry. that was rude.

14:19 <alyssa> but GPU register allocation is -not- "way more regular", unfortunately.

14:19 <alyssa> if anything it's worse depending on the architecture

14:19 <alyssa> Bifrost is ok, but something like Midgard?

23:50 <newton688> Hi All, I'm seeing some strangeUI problems on my Pinebook Pro and getting some panfrost error messages that seem could be correlated. Would sharing my logs and steps to reproduce the problem be helpful?