alyssa changed the topic of #panfrost to: Panfrost - FLOSS Mali Midgard & Bifrost - Logs https://freenode.irclog.whitequark.org/panfrost - <daniels> avoiding X is a huge feature
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<icecream95> It seems that any value for hierarchy_mask with eight or less bits set works, but if more bits are set it DATA_INVALID_FAULTs
<alyssa> icecream95: Technically that's implementation defined, it's definitely true for G72 and G76 though.
<alyssa> G31 and G52 might be special, iirc we saw issues with this a while back.
<alyssa> icecream95: I believe the limit 1 <= bitcount <= 8 applies to all Midgard, however.
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<robmur01> G31 certainly, according to its feature registers
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<robmur01> probably G52 as well; the documentation is slightly inconsistent but it looks like a copy/paste error
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<HdkR> https://www.geniatech.com/product/sdm3399/ My goodness it's adorable
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<chewitt> @HdkR is easily pleased :)
<HdkR> I like cute hardware
<HdkR> The idea of having rack mounted ARM devices for my CI machines would be nice
<chewitt> but .. Geniatech
<chewitt> "ships with Android 7.1" .. is all you need to know about their attention to details
<HdkR> Yea. Can't really use Android for CI :P
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<robmur01> Eh, but who needs individual ports? You can go even denser by just cramming boards into drawers :P - http://en.t-firefly.com/product/cluster/r2.html
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<urjaman> Ubuntu isnt linux anymore i see
<HdkR> Sadly 72 RK3399 boards is a different type of scaling than what I'm looking for :P
<HdkR> Hoping for sometihng like Neoverse V1 upgrade to the Honeycomb LX2K board. Planning on a couple Orin Jetsons...
<HdkR> Or N2 I guess
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<HdkR> Dang it, now I'm sleepily looking at how to deploy ctest things across a cluster. Nope. nooooope
<amonakov> on Bifrost, is a "warp" dispatched simultaneously to "lanes", or is it dispatched to one lane on consecutive cycles (and therefore different lanes handle different warps)?
<amonakov> we've investigated instruction issue on g72 and g76 a bit, and from what we see, each pipe can accept an instruction from a particular thread each 12'th cycle
<amonakov> which makes sense on g72 with 4-wide warps (cycles over 3 warps per lane), but doesn't on g76 (8-wide warps); apparently on g76 "each 12'th cycle" becomes "each 16'th cycle" in case there's another warp
<amonakov> this is a bit of a mindfuck, but I suspect this would not be the first time "Mali" and "crazy" go hand in hand
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<robmur01> hopefully you've come across this before, but just in case: https://www.anandtech.com/show/10375/arm-unveils-bifrost-and-mali-g71/2
<amonakov> yeah, I had, thanks
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<cwabbott> amonakov: all lanes are dispatched at the same time, the "every 12'th cycle" bit probably comes from the pipeline depth
<cwabbott> from the ISA's perspective, each instruction starts immediately after the previous one finishes
<cwabbott> specically the write stage of an instruction overlaps with the read stage of the next
<amonakov> cwabbott: but for simultaneous dispatch to work, the core would need to cycle over 12 warps to cover that, and t registers would need to be queues of about 6 entries or so
<cwabbott> obviously everything in between doesn't happen in one cycle, so instructions for each thread are only dispatched on every n'th cycle where n depends on the pipeline depth (and apparently is 12 on g72) and you need n quads/waves active at the same time to keep it fed
<cwabbott> yes, that's exactly right
<amonakov> how can you tell the dispatch is simultaneous and not [the other approach I described]?
<cwabbott> that's what ARM's docs say
<cwabbott> also derivatives probably wouldn't work well that way
<cwabbott> sorry, that's what the anandtech article says
<cwabbott> (i don't have access to ARM's docs)
<amonakov> I am not entirely convinced, since then we'd observe that 12 warps are enough to saturate a g76 core, and yet that's not the case
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<amonakov> but we also found a related difficult-to-explain effect on g76, so who knows... I'll try to run more experiments
<amonakov> one more reason I am having doubts is that on Nvidia selecting a warp is known to have a cost, so it is surprising that Mali would be engineered to select one of 12 warps on each cycle like it's no big deal
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<amonakov> (correction, 12*3 warps since there are 3 sets of lanes per core; on g72 36 4-wide warps do saturate)
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<amonakov> (and to clarify one more thing, 12 cycles would be the sum of MUL and ADD pipe latencies, not their individual depths)
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<alyssa> amonakov: it also might be that g76 and g72 are dramatically different uarchs
<alyssa> (I don't know if this is the case)
<alyssa> there is no 'promise' of stability between major archs
<amonakov> anandtech covered g76 in another article, and it mostly enumerated differences without saying there was a major redesign
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<alyssa> amonakov: It's a different major arch (G71/G72 vs everything else) so who knows
<amonakov> I am not making assumptions about G76 based on G72 data, or vice versa; we ran the same experiments on both
* alyssa probably misread your results then
<alyssa> It has been a very long week and it's only Wednesday 😿
<urjaman> I had that mood already at the end of monday
<icecream95> wdym it's only Wednesday?
<macc24> it is wednesday my dudes
<icecream95> [looks outside] Nope, definitely a Thursday
<macc24> *looks at clock* 30 minutes of wednesday left for me
<macc24> i'd surely have more wednesday if i didn't sleep through it
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