ChanServ changed the topic of #picolisp to: PicoLisp language | Channel Log: https://irclog.whitequark.org/picolisp/ | Check also http://www.picolisp.com for more information
_whitelogger has joined #picolisp
lodsw has quit [Ping timeout: 245 seconds]
lodsw has joined #picolisp
Blue_flame has joined #picolisp
_whitelogger has joined #picolisp
xkapastel has joined #picolisp
Green_flame has joined #picolisp
Red_lizzard has joined #picolisp
Red_lizzard has quit [Client Quit]
Blue_flame has quit [Ping timeout: 248 seconds]
Green_flame has quit [Ping timeout: 260 seconds]
<Regenaxer> tankf33der: I give up rewriting the case mappings. Instead, I reuse the C version from pil32.
<tankf33der> ok
<Regenaxer> Uppercase sharp S is not needed, I understand that it is not used normally
<Regenaxer> If we find a flaw, or a better version, we can replace the C code
_whitelogger has joined #picolisp
razzy has quit [Ping timeout: 260 seconds]
Retropikzel has joined #picolisp
xkapastel has quit [Quit: Connection closed for inactivity]
Retropikzel has quit [Quit: Vision[0.10.3]: i've been blurred!]
xkapastel has joined #picolisp
libertas has quit [Ping timeout: 240 seconds]
_whitelogger has joined #picolisp
xkapastel has quit [Quit: Connection closed for inactivity]
Retropikzel has joined #picolisp
Retropikzel has quit [Ping timeout: 245 seconds]
razzy has joined #picolisp
<razzy> can i work with L1 L2 L3 caches from x86 ASM and use L1 L2 L3 as fast RAM? or are caches semi autonomous and not in programmer controll
<tankf33der> razzy: try to search on stackoverflow
<Regenaxer> I think they are not controllable by the programmer
<Regenaxer> Caches are used automatically by the hardware
<Regenaxer> So they *are* already a fast RAM, used in an optimal way
libertas has joined #picolisp
jibanes has quit [Ping timeout: 240 seconds]
jibanes_ has joined #picolisp
orivej has quit [Ping timeout: 268 seconds]
orivej has joined #picolisp
xkapastel has joined #picolisp