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<vrand>
Hey, all! Working on random exercises to get a further feel for the language. Right now I'm implementing a Fibonacci calculator but my implementation is super slow. Here's the code along with my specs and the results — https://gist.github.com/vrand/e691cd3d312c6cfca9c93c7ffc481d53
<vrand>
Any suggestions on optimizing or a fundamental thing I'm not grasping?
<vrand>
(or are my expectations just incorrect for the time taken to compute)
<vrand>
Nice! I'll play with that and see how they compare.
<vrand>
Thanks
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<Praetonus>
vrand: I'd suggest you to use a tail-recursive function or a loop. The "naive" fibonacci implementation is one of the worst recursive pattern for performances in procedural languages
<lisael>
vrand: in this file I've cheated in fibonacci calls, I compute fib(40) fib(200) and fib(500) depending on the method. some are very slow and other much faster I had to cheat. to see a meaningful result.
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<SeanTAllen>
i have a perf issue to look into where it appears turning a U64 into a string is oddly slow and slower than it should be so doing U32 instead might also help BUT you need to be at pretty high levels of usage for that to be very noticable
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<Praetonus>
TwoNotes: Regarding the ARM bug, is your processor 32bits or 64bits?
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<TwoNotes>
Praetonus, 32
<TwoNotes>
armv7l
<TwoNotes>
btw, since putting in the mutex code I have not had any crashes, allowing me to finally make progress on other features. Before it could not stay up long enough
<Praetonus>
Then I think I know what is wrong. ponyint_mpmcq_pop is doing a double-word compare-and-swap. It's supposed to be on 128bits but on a 32bits system it's on 64bits. We talked about it during the sync meeting yesterday and there may be people in the community able to confirm that and maybe find an efficient solution
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<TwoNotes>
I was not able to attend that. Good that there is progress.
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<TwoNotes>
I did a little test where I did a normal fetch both before and after the _atomic_load, and compared them
<TwoNotes>
They would compare equal, but still the value fetched from _atomic_load would be something odd
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<TwoNotes>
I notice that the "DMB ISH" instruction only interlocks the "inner sharable" memory doain, but exactly what this is depends on the specific machine architecture.
<TwoNotes>
Hmm. What I have is an Rpi3. The press releases back in February said it had a "quad-core 64-bit ARM Cortex A53" cpu, which is an ARMv8-A. But the uname command says armv7l. The Arch Linux system, since it is running in 32b mode, may be lying about the architecture version
<TwoNotes>
But I would bet that the behavior of the memory barrier commands followed what the v8 spec says
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<TwoNotes>
archlinuxarm.org says that a future release will run in 64b mode
<Praetonus>
Is the CPU word size affected by that? E.g. would a ldrd instruction on your system load 64bits?
<vrand>
I don't understand much but I like listening to them :)
<TwoNotes>
Yes, I have that. tnx
<vrand>
Ah ok!
<TwoNotes>
I havnt listend to it yet
<vrand>
The ARM bit was near the end, last 8ish mins
<TwoNotes>
I used to be into all that hardware stuff back in college. But for the last few decades my interests have been in network protocols rather than bit twiddling
<TwoNotes>
I have listened to that segment now. It sounds like this should be fixable in a more elegant way
<Praetonus>
I hope. A mutex here really isn't good
<TwoNotes>
Kind of a sledge hammer
<Praetonus>
Could you make a gist with the assembly code for ponyint_mpmcq_push?
<TwoNotes>
In the declaration for the typedef mpmcq_dwcas_t, there is a ", 16" at the end. I am not familiar with that notation. What does the 16 mean?
<Praetonus>
It's the second argument for __pony_spec_align, which specifies an alignment for the type