<gatecat>
Lofty/Sarayan: so, I'm trying to get a better grip on the cyclone v arch so I can help get the nextpnr skeleton up and running (and I think understanding things better might help with the interchange stuff too). A couple of initial questions
<gatecat>
did we ever work out whether the DATAA etc pins are shared between the top and bottom halves, or separate?
<gatecat>
I remember some discussions about that a while ago but don't know if they reached a conclusion
<gatecat>
also, I'm looking at the clock routing for a simple design and it seems like the IO->global clock part doesn't use the general routing mux structures but is a special config entry "s CMUXVG.042.000:INPUT_SELECT.2 00" - is there anything in mistral that maps what those INPUT_SELECTs actually correspond to (pins, I expect there might be other sources too)
<gatecat>
OK, I think the answer to my first question is "in the actual routing graph they are the same node, Quartus can sometimes pretend they are separate because of permutation magic"
<gatecat>
this is definitely gonna be fun to capture in nextpnr...
<Sarayan>
I'm back
<Sarayan>
ok, when you says DATAA, you mean of LABs?
<Sarayan>
and yes I need to add the clock mux routing info in libmistral, I have it in notes but not in the code yet
<Sarayan>
gatecat gatecat gatecat :-)
<gatecat>
hi! yeah I do mean the LABs
<Sarayan>
each LABCELL has its own 8 inputs
<Sarayan>
ABCD E0 F0 E1 F1
<Sarayan>
clock sources are pins, plls, or can come from the data routing grid
<gatecat>
excellent, I think clock muxes will have to be another special kind of pip inside nextpnr (along with general routing and the ALM internal muxes)
<Lofty>
gatecat: annoyingly "Lofty/Sarayan" doesn't ping me, otherwise I would have replied ;~;