cfbolz changed the topic of #pypy to: PyPy, the flexible snake (IRC logs: https://botbot.me/freenode/pypy/ ) | use cffi for calling C | "the modern world where network packets and compiler optimizations are effectively hostile"
<kenaan>
cfbolz default 0f01249125f8 /rpython/jit/backend/x86/assembler.py: make jit-backend-counts not be empty if it's the only section asked for
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<kenaan>
arigo cffi/cffi 2763112dfca7 /c/lib_obj.c: Should call GC_UnTrack before Py_DECREF()
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<kenaan>
cfbolz default f59f82d01a6d /rpython/jit/backend/llsupport/regalloc.py: simplify the logic
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<kenaan>
cfbolz regalloc-playground 32c23f8fb859 /rpython/jit/backend/: a branch to try out some register allocation ideas first step: refactor lifetime storage to not be tu...
<kenaan>
cfbolz regalloc-playground 39a4798dc769 /rpython/jit/backend/x86/test/test_x86vector.py: fix test
<kenaan>
cfbolz regalloc-playground beea904fa30e /rpython/jit/backend/llsupport/regalloc.py: some ideas what to improve
<kenaan>
cfbolz regalloc-playground b4d4200219d6 /rpython/jit/backend/: store the last_real_usage on the Lifetimes as well
<kenaan>
cfbolz regalloc-playground c5b3232137fe /rpython/jit/backend/llsupport/: spill variables that are no longer "really" used (ie appear only in failargs or jumps)
<cfbolz>
but the second condition should just be removed
<cfbolz>
it's implied
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<cfbolz>
my first hack for register allocation improvements gives 10% speedup on some benchmarks
<cfbolz>
(and is neutral on the other things I measured)
<LarstiQ>
what are the improvements?
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<cfbolz>
LarstiQ: just a small improvement in what registers are spilled
<LarstiQ>
cfbolz: more of a detail tweak than different algorithm?
<arigato>
cfbolz: good
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<arigato>
cfbolz: we don't record optimization info for "int_is_true" because we can't store "!= 0" as a single range
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<cfbolz>
arigato: yes, but we could record it as a pure op
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<cfbolz>
Eg when we see an int_add we also remember the equivalent int_sub op
<cfbolz>
We could do the same here
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<arigato>
er, maybe
<cfbolz>
I put it on my todo
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<arigato>
ok
<cfbolz>
arigato: I red register allocation papers during my location. I learnt that we are basically already doing linear scan, at least a basic version.
<cfbolz>
Vacation
<cfbolz>
So what's left to do is to add a few of the tweaks (some are super complex, but simple versions we can just do)
<cfbolz>
Still not fully clear whether we can expect much performance improvement
<arigato>
yes, I still have no clue whether improving only register allocation will give us 0% or 20% better performance
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<cfbolz>
arigato: indeed
<cfbolz>
If it's 10% I would be happy
<cfbolz>
LarstiQ: yes, basically it turns out that detail tweaks are the only difference between us and 'real' JITs
<cfbolz>
Tons of them, of course
<LarstiQ>
cfbolz: right
<LarstiQ>
and some fiddly ones from what you said above
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<arigato>
rvmprof broke again by changing its API
<arigato>
this time, in Monte
<simpson>
Whoo! Yeah, I haven't touched the vmprof on our side for like a year?
<simpson>
Also I think we still have the really really hacky thing where we create fake frame types or something like that.
<simpson>
So maybe whatever we did is just not kosher.
<arigato>
possibly, but now rvmprof generates invalid C code if we use the decorator @rvmprof.vmprof_execute_code more than once
<simpson>
That sounds like a problem.
<arigato>
hum, and *also* if we call it zero times but we still import rvmprof
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