azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing |,, | Logs:
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<azonenberg> tnt: so i got the crc working and i didnt have to use the decomposition trick
<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-2/±0]
<_whitenotifier-f> [starshipraider] azonenberg 070e7bc - Removed redundant simulation for architecture that never got used
<azonenberg> a fully unrolled 128 bit implementation actually made timing, the only hard part was doing partial words
<azonenberg> i ended up using a pipelined design that contained 3 stages at the end
<azonenberg> 64 bit, 32 bit, and 0/8/16/24 bit variable width
<azonenberg> it's 877 LUT, 436 FF, and makes timing on a -2 kintex7
<tnt> azonenberg: oh nice.
<tnt> Do you know the max logic depth (in LUTs) ?
<azonenberg> my plan right now is to do all of my design work and timing signoff on a -2 speed
<azonenberg> but build the first two prototype maxwell boards with a -3
<azonenberg> so i have a bit of margin i can pull out if i run into problems later on
<azonenberg> The critical path right now is in the variable width crc, from the input data register through the crc logic and then a mux specifying whether we're using the variable width path at all or not
<azonenberg> Six levels... a lut2, a lut3, and four lut6s
<azonenberg> 767 ps logic, 2172ps routing
<tnt> damn, fpgas have gotten faste ;)
<azonenberg> So now i think i'm going to get back to the rx side of my 40G MAC and start building out the IP stack
<azonenberg> with a short detour later in the week to prep some boards for ordering
<azonenberg> well, supplies
<azonenberg> i'm ordering the production MEAD enclosures so i need to finalize the design, the prototype batch had problems where the screw holes weren't drilled deep enough
<azonenberg> they were drilled to spec but i hadnt specified enough depth for the length of my screws
<azonenberg> so i need to either find shorter screws or update the cad design to have deeper holes, or both
<azonenberg> then i also need to finalize the design of the new AKL-PT2 PCB with soldermask, as well as the mold for the silicone potting
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