08:14 <mkk_> [Tayyeb Mahmood, skywater-pdk] Hi all, can anyone guide me whether it is possible to leverage multicore processing in baking with openlane? Currently, my flow is using one CPU only.

12:47 <mkk_> [Philipp Gühring, skywater-pdk] Tayyeb: There is an #openlane channel dedicated for openlane. From my point of view, openlane consists of many smaller tools that are mostly executed sequentially, so it depends on each of the tools do use multiple cores. I wouldn't be surprised if parts of it would run in parallel and parts of it only on one core.

13:05 <mkk_> [Dan Ravensloft, skywater-pdk] Yosys for synthesis is inherently single thread, and you'd have to entirely rewrite it to make it thread-safe.

13:29 <mkk_> [Tayyeb Mahmood, skywater-pdk] Thanks @Philipp Gühring and @Lofty, now I got that only Detailed routing supports multicores, other parts are single threaded.

13:41 <lkcl> Donn: all good! website issue sorted.

13:42 <lkcl> the other question was about caravEL (not caravan, carav*el*) which hasn't had an announcement yet (i'm on the mailing list)

13:43 <lkcl> i do appreciate it's extremely new, however i do not have access to the slack channel the initial announcement went out on

13:47 <lkcl> basically we will be using Chips4Makers FlexLib, ported to the Skywater 130nm PDK, and would like to test the FlexLib IO Cell Library (in 130nm), FlexLib Standard Cell Library (in 130nm) and the FlexLib SRAM Cells, which *may* end up being auto-generated

13:48 <lkcl> caravan is not appropriate for that, and i wondered if caravel is

13:48 <lkcl> specifically: will caravel be an analog *only* process, or will it allow digital?

14:06 <mkk_> [Manar Abdelatty, skywater-pdk] caravan is for analog projects. caravel is for digital projects

14:27 <mkk_> [Philipp Gühring, skywater-pdk] Caravan is having several unprotected IOs which are usable for analog projects, but it also has protected IOs which are suitable for digital, so it can be used for both analog and mixed signal projects.

14:30 <lkcl> ok, great. so what if we wish to test the creation of an entire independent ASIC which does not have the "Management Core", at all?

14:30 <lkcl> we have our own Libre-Licensed PLL (developed by Sorbonne University)

14:31 <lkcl> and the Cell Libraries from Chips4Makers

14:31 <lkcl> and would like to test those Cell Libraries - including the IO Cells - in 130nm.

14:31 <lkcl> how would that work?

14:45 <mkk_> [Philipp Gühring, skywater-pdk] Do you want to be on a Google Shuttle?

14:45 <lkcl> Philipp: ideally, yes

14:46 <mkk_> [Philipp Gühring, skywater-pdk] In that case, you have to make sure that your IO's are at the exact same place as the ones on the Caravel/Caravan chip, and you have to fulfill a few other compatibility requirements.

14:47 <lkcl> not a problem - we just need to know what those are.

14:47 <lkcl> we'll be generating DRC-clean GDS-II files

14:48 <lkcl> the Caravel/Caravan positions are in the online repo, i assume?

14:48 <mkk_> [Philipp Gühring, skywater-pdk] @Tim Edwards has written about those compatiblity requirements before, I am not sure whether I will find them now ...

14:49 <lkcl> was it in the irc channel (or the slack-channel-relayed-to-irc)?

14:49 <lkcl> if so i should be able to search back through the irc logs

14:49 <lkcl> https://github.com/efabless/caravel

14:50 <lkcl> so that repo _should_ contain the exact positions of the IO

14:53 <mkk_> [Philipp Gühring, skywater-pdk] There are several Slack channels that are relayed to IRC, unfortunatley I couldn't find it right now, so please search yourself on Slack directly

14:54 <mkk_> [Philipp Gühring, skywater-pdk] You could also take a fully generated GDS-2 and measure the exact positions there, perhaps?

14:57 <lkcl> Philipp: company policy prevents me from joining slack.

14:57 <lkcl> yes, that same thought occurred to me

14:57 <lkcl> i just found these: https://github.com/efabless/caravel/tree/master/gds

14:58 <lkcl> that should be easy to do, i have klayout built.

14:58 <lkcl> thanks

15:14 <mkk_> [Tim Edwards, skywater-pdk] Officially we do not support projects that do a wholesale replacement of the caravel chip. It will not run through the standard submission process; supporting it therefore requires an extra effort on our part which we don't have the time and staff to support. If you are testing a padframe, the best thing to do is to build an entire chip that fits inside the user project area. A couple of projects di

23:11 <mkk_> [Matt Liberty, skywater-pdk] @Tayyeb Mahmood I see there is a ROUTING_CORES variable to control TritonRoute threading which is likely to be the most time consuming step