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Title: GitHub - maximuska/depslint: A tool for dependencies validation for ninja build system using strace to detect the real dependencies (at github.com)
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<rajesh-s>
hello
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<daveshah>
mithro: ack, will investigate over the weekend
<mithro>
daveshah: _florent_ just said "The timings have been improved and the Host now receives correctly the TSEQ/TS1 from the Versa ECP5. I still need to look at the RX path, but we should not be far from being able to use the Versa ECP5 for the dev."
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<_florent_>
daveshah, mithro: i was expecting these timing violations, this was a first report without any optimizations. TX is now fine, RX is not far but i just spend a few minutes looking at it, i need to spend more time. The timings issue seems to be around the 8b10b decoder (which is done in the fabric), i'll probably need to do some optimizations
<daveshah>
Is there a reason you aren't using the hard 8b10b?
<mithro>
_florent_: Yeah - I was just pointing daveshah to someone doing something cool with the ecp5
<_florent_>
daveshah: yes, i just want to use the serdes as simple serializer/deserializer (as we are doing with others FPGAs), and this is also useful to generate LFPS
<_florent_>
daveshah: but if it's really causing timing issues, i'll probably switch to the hard ones
<daveshah>
_florent_: ack, I think there is some OOB functionality that could be used for LFPS
<mankeli>
any idea when that ECP5 tinyfpga is coming and how much it will cost?
<mankeli>
since it has serdes, it should be capable of hdmi right?
<daveshah>
The SERDES isn't actually a very good match for HDMI
<daveshah>
Wrong signalling level
<daveshah>
If you only need 720p60 or 1080p30, regular ECP5 IO pins are actually a better choice
<mankeli>
no? I have used serdes (although friend did the ip) on zynq7 for hdmi
<daveshah>
Ah, paths are crossed here
<daveshah>
"serdes" in Xilinx sense is presumably referring to IO SERDES primitives, ie still regular IO pins
<mankeli>
ah
<daveshah>
There's also the high speed transceiver for PCIe, USB3, etc (GTX/GTH/etc in Xilinx)
<_florent_>
daveshah: btw, i added SCI support to have more control on the serdes parameters
<daveshah>
Very nice
<daveshah>
That should make tuning easier
<mankeli>
it's the OSERDESE2 primitive that does the diff serial output
<daveshah>
So the ECP5 doesn't have an exact equivalent to that
<daveshah>
But it has ODDRX2F which is the same as an OSERDESE2 in 4:1 DDR mode
<daveshah>
Unfortunately no 10:1 or 8:1 mode
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<mankeli>
there's some document describing hdmi on ECP3 using "CML SERDES", is that something different than what the ECP5 has?
<daveshah>
As far as I know, the only options for HDMI on ECP5 are the transceivers (Lattice call them SERDES, GTX in Xilinx world) with a level shifter; or regular IO pins and a 4:1 gearbox (SERDES in Xilinx world)
<daveshah>
But the latter option can't do 1080p60
<daveshah>
That app note seems to be using a level shifter