00:51 <mithro> kgugala: I created https://github.com/SymbiFlow/python-symbiflow-v2x

00:51 <tpb> Title: GitHub - SymbiFlow/python-symbiflow-v2x: Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow. (at github.com)

00:52 <mithro> lromor[m]: How did you hear about the project?

00:53 <lromor[m]> thanks to hzeller , we met at ccc.

00:53 <mithro> lromor[m]: I think we probably met at CCC then too?

00:54 <lromor[m]> yup! We had lunch toghether

00:55 <lromor[m]> not sure if you remember my face: https://github.com/lromor

00:55 <tpb> Title: lromor (Leonardo Romor) · GitHub (at github.com)

01:08 <mithro> lromor[m]: Do you think you'll have much time to contribute?

01:21 <lromor[m]> <mithro "lromor: Do you think you'll have"> I probably won't have too much time but maybe I'll manage 8h a week. I'm very interested in the topic for multiple reasons. I'm currently busy as a student, but I would be more than happy to be able to contribute in my free time.

01:21 <mithro> lromor[m]: What level of student?

01:23 <lromor[m]> <mithro "lromor: What level of student?"> It's my second Master, I'm currently starting the second year of an MSc in artificial intelligence. Soon I'll start my thesis.

01:24 <mithro> Going to use FPGAs for that?

01:32 <lromor[m]> I don't know the details yet of the project, but might be related to implementing and benchmarking a better algorithm for convolutions and compare it with the one provided by gpu vendors, using fpgas as third accelerator for comparison would be super cool. Also right now it's maybe missing a opencl to fpga converter, that would be a great project! I feel my current knowledge of fpga is too small right now to assess the

01:32 <lromor[m]> true potential in the AI field but I'm definitely interested in discovering it.

01:36 <lromor[m]> <lromor[m] "I don't know the details yet of "> I think I could try to sell it to my supervisor :P

02:28 <hackerfoo> mkurc: I rebased and force-pushed to the x1y0 branch, so please rebase if you're working on that branch.

14:23 <sf-slack3> <mkurc> @hackerfoo @litghost I made a generic IOB33_MODES pb_type referenced by the IOB33M pb_type. I also updated the document with out ideas about the ROI breakout.

16:58 <hackerfoo> "Starting with Vivado 2019.1, Partial Reconfiguration is included at no

16:58 <hackerfoo> additional cost within all Vivado Editions, including WebPack."

16:58 <hackerfoo> https://www.xilinx.com/products/design-tools/vivado/implementation/partial-reconfiguration.html

16:58 <tpb> Title: Partial Reconfiguration in the Vivado Design Suite (at www.xilinx.com)

19:18 <lromor[m]> Hi, I was reading about the roi_harness minitest. `Creates an harness bitstream which maps peripherals into a region of interest which can be reconfigured.`

19:18 <lromor[m]> Is it correct to say that right now, that fuzzers are made in order to, given an input to vivado, get an output bitstream which is then reverse engineered? Minitests looks like a way to test that such reverse engineering assumptions hold. About the roi_harness, my guesses it that its's necessary since it's maybe uknown how the IOBs work right? So you first map with vivado a pin to a (CLB?) to proxy the signal. Is

19:18 <lromor[m]> anything that I just wrote correct?

19:24 <sorear> at the time roi_harness was created, it was unknown how IOBs worked. I don’t know if this is still the case but it was correct at the time

19:31 <litghost> I think it is simplier to say that we wanted to be able to make progress without worrying about how the IOBs functioned. Even now that we have all the relevant IOB bits, we still rely on the harness. The signals in the harness is simply brought a point in the routing graph that is unoccupied (e.g. VBRK tiles), and we attach our smaller routing graph at these points

20:00 <lromor[m]> thanks!

20:00 <lromor[m]> How could I help you removing the harness? =P

20:01 <litghost> HackerFoo and mkurc are actively working on it. I'll let them suggest if there is a way to do so.

20:12 <hackerfoo> lromor[m]: Are you comfortable with Python?

20:12 <lromor[m]> aye sir, very less with cmake though

20:12 <lromor[m]> * @freenode_hackerfoo:matrix.org aye sir, very less with cmake though

20:13 <lromor[m]> * @freenode_hackerfoo:matrix.org aye sir, much less with cmake though

20:21 <hackerfoo> Each time you edit your message it sends a new one over IRC.

20:22 <hackerfoo> lromor[m]: I'll send you the pull request so you can look it over. There are a few hacks for which maybe you could provide a more elegant solution, if you want.

20:23 <daveshah> FWIW, ROI escape is definitely now possible with Xray, I even got a proof of concept working with nextpnr

20:23 <lromor[m]> Oh I see, I was wondering indeed, I'm sorry. I'll avoid that.

20:23 <daveshah> https://github.com/daveshah1/nextpnr/tree/rapidwright-xc7

20:23 <tpb> Title: GitHub - daveshah1/nextpnr at rapidwright-xc7 (at github.com)

20:24 <daveshah> (this uses Xray for bitgen only though, not database)

20:27 <hackerfoo> lromor[m]: What is your GitHub username?

20:28 <lromor[m]> hackerfoo: lromor

20:29 <hackerfoo> TIL GitHub is case sensitive.

20:32 <lromor[m]> hackerfoo: ha️

20:33 <hackerfoo> lromor[m]: I guess I can't add you as a reviewer yet, but here's the PR: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1011

20:33 <tpb> Title: Add IO for X1Y0 by HackerFoo · Pull Request #1011 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

20:37 <lromor[m]> Thanks, I'll go through it!

21:01 <hackerfoo> litghost: https://gist.github.com/HackerFoo/5be503f6d09da339654d2a97d3040cd9

21:01 <tpb> Title: design.json · GitHub (at gist.github.com)