17:00 <mithro> kgugala: Possible interesting stuff for you -> https://github.com/Elphel/vdt-plugin/blob/master/parsers/parser_ise.py

17:00 <tpb> Title: vdt-plugin/parser_ise.py at master · Elphel/vdt-plugin · GitHub (at github.com)

17:00 <mithro> kgugala: Possible interesting stuff for you -> https://github.com/leaflabs/xmsgs-tools

17:00 <tpb> Title: GitHub - leaflabs/xmsgs-tools: little python helpers for parsing through Xilinx build outputs (at github.com)

17:19 <sf-slack3> <kgugala> @mithro thx, I'll take a look on those

19:32 <hackerfoo> VPR is packing both the input and output pads in the same IOPAD. How do I prevent this? I could use modes for now, but this will prevent input and output on the same pin.

19:34 <hackerfoo> I think I need a third mode with an IOBUF.

20:43 <sf-slack3> <mkurc> @hackerfoo: Is that an error? Because from my understanding that is how actually an input/output pin should work in VPR.

20:46 <hackerfoo> mkurc: If I make a simple `assign out = in` design, both pins would get packed together before they get a chance to be placed based on the PCF/io.place.

20:47 <hackerfoo> Then it's too late, because there is only one cluster.

20:47 <sf-slack3> <mkurc> oh

20:49 <hackerfoo> So it's an artifact of thel separation of phases.

20:49 <hackerfoo> *the

20:53 <sf-slack3> <mkurc> So maybe try inserting a LUT there. Try `assign out = !in` That should translate into a LUT and in turn force VPR to separate nets for those pins

21:13 <hackerfoo> VPR routes now with modes for IBUF/OBUF if I manually edit top_io.place, so now I need to change prjxray_create_ioplace.py to lookup the block names in top.net.