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<hackerfoo> I got the site->site interconnect working in IOPAD. I'm trying to get IBUF/OBUF techmapped, but got stuck on a "Can not find any logic block that can implement molecule" error: https://github.com/SymbiFlow/symbiflow-arch-defs/commit/b3e82269317da9fe8c2c9f547e3d074ee7cdfddf
<tpb> Title: WIP techmap IBUF/OBUF primitives · SymbiFlow/symbiflow-arch-defs@b3e8226 · GitHub (at github.com)
<hackerfoo> Any idea what I'm doing wrong?
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<sf-slack3> <mkurc> @hackerfoo Well, it works for me. I started with a clean build directory.
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<sf-slack3> <acomodi> I have successfully routed and created a bitstream using the BUFG and BUFHCE primitives. The only problem now is that it does not run on HW
<sf-slack3> <acomodi> The test I have been doing is `counter_basys3`. What happens is that some random leds are switched on (and they are not supposed to be) and there is no blinking happening.
<sf-slack3> <acomodi> My thought is that there is an issue when generating the frames as maybe the roi_harness is overlapped with the generated FASM, hence the strange behavior of the leds.
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<sf-slack3> <mkurc> @hackerfoo: I'm currently working on making prjxray_tile_import.py import all sites and generate correct fasm prefixes for them. I'll try to finish by the end of the day.
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<sf-slack3> <mkurc> @hackerfoo: I've pushed my changes. The import works except for the inner_pins which is broken now (interconnect generation)
<hackerfoo> mkurc: Why did you decide to un-split (Y0/Y1) IOPAD? My understanding (from talking to litghost) is that this will make it difficult to select between the two pads in an IOPAD.
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<litghost> acomodi: I would definitely run bit2verilog on your results and see what is going on
<litghost> hackerfoo: Did you resolve you packing issue?
<hackerfoo> litghost: No
<hackerfoo> mkurc: Adding back "SELECT_Y 1" fixes the build.
<litghost> hackerfoo: Which packing step is failing? wire.eblif?
<hackerfoo> Yes.
<litghost> hackerfoo: So wire.eblif assumes that "assign out = in" will work. We can simulate that same way we support a passthrough ILOGIC, with a mode that defaults to a straight wire
<litghost> hackerfoo: Does that make sense?
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<hackerfoo> I changed wire.eblif, though (commented out right now): https://github.com/SymbiFlow/symbiflow-arch-defs/commit/b3e82269317da9fe8c2c9f547e3d074ee7cdfddf
<tpb> Title: WIP techmap IBUF/OBUF primitives · SymbiFlow/symbiflow-arch-defs@b3e8226 · GitHub (at github.com)
<litghost> so the out pad of the IOPAD is IOI3 routing interface <OLOGIC mode passthrough/ODDR/OSERDES> <OBUF mode passthrough/OBUFT>, etc
<litghost> hackerfoo: Changing wire.eblif will break non-7-series (e.g. testarch and ice40), so that is not a great long term solution
<hackerfoo> So I should add a mode without IBUF/OBUF?
<hackerfoo> That should work.
<litghost> hackerfoo: It might not hurt, and but it will need to emit FASM as if there was an IBUF/OBUF
<hackerfoo> I have the interconnect working between {I,O}LOGIC and IOB33M now.
<hackerfoo> Yeah
<litghost> hackerfoo: E.g. the prjxray_tile_import is making the connections?
<hackerfoo> Yes
<hackerfoo> Just using a predefined map for now.
<tpb> Title: add IOPAD site->site interconnect to prjxray_tile_import.py · SymbiFlow/symbiflow-arch-defs@ad4560c · GitHub (at github.com)
<hackerfoo> I plan to add a script to generate the map at some later point.
<hackerfoo> From tileconn.json + channels.db
<litghost> hackerfoo: There shouldn't be a need to use tileconn.json at all
<litghost> hackerfoo: The nodes are present in channels.db
<hackerfoo> It is, but it's elaborated *too* much, there are nodes for every IOI<->IOB tile edge. I only need one.
<hackerfoo> I could still write a query, even if it's slow. Or maybe pick an arbitrary pair of tiles.
<hackerfoo> It might be worth splitting nodes by direction, and precomputing for each tile pair, at least when they only cross the tile in one direction.
<hackerfoo> Not now, though.
<hackerfoo> *tile type pair
<litghost> > there are nodes for every IOI<->IOB tile edge. I only need one.
<litghost> I'm not sure your conclusion is valid. For any given site pin on an IOB or IOI, how do you know if it connects to another site pin?
<hackerfoo> Don't IOBs and IOIs always connect the same way, at least on the same side of the chip?
<litghost> hackerfoo: The whole exercise is to not assume a structure, but infer the right thing from the underlying data
<litghost> hackerfoo: Consider that there may be variation across other chips
<hackerfoo> The same structure is in the DB, in tileconn.json
<litghost> hackerfoo: There is also some form of variation within the chip, with the TTERMBYTE, etc
<hackerfoo> Yeah, but that's a different tile-type pair.
<litghost> hackerfoo: tileconn.json only provides adjacent tile information, if there is every an intermediate tile, then tileconn is unsuitable for the query you want
<hackerfoo> At least, nodes-per-tile-type pair would have been exactly what I need for this task.
<hackerfoo> I can just pick a tile pair, though. That should work, since they will all be the same.,
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<sf-slack3> <mkurc> @hackerfoo: I did the un-split because in the end we will need to use both IOBs and they have to be in the same tile. Unless we want to merge IOB+IOI and then split the resulting tile horizontally...
<sf-slack3> <mkurc> setting SELECT_Y fixes the build because when on there is only one site of each kind
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<litghost> mkurc: I don't believe for differential IO we want 1 cluster
<litghost> mkurc: I believe we want two clusters that share a relationship, either via place macro (e.g. direct inter-tile connection) or via placement io constraints
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<hackerfoo> mkurc: My intention was to use SELECT_Y to make IOPAD_Y0 and IOPAD_Y1, and then we can make those tiles equivalent.
<hackerfoo> But for now to just work on one of them.
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<hackerfoo> litghost: Do you know where I should look to get Yosys to infer IBUF/OBUFs?
<litghost> hackerfoo: http://www.clifford.at/yosys/files/yosys_manual.pdf write_blif "-buf <cell-type> <in-port> <out-port>" is the way I know off the top of my head
<litghost> hackerfoo: It is unclear how to tell yosys "use this if not that"
<litghost> hackerfoo: I think the way to do it may be "emit IBUF/OBUF always, and then merge doubled buffers"
<litghost> hackerfoo: But that is a good question for #yosys
<litghost> hackerfoo: I'm no expert on this particular aspect
<hackerfoo> litghost: Thanks
<hackerfoo> litghost: Do you know what this means?
<hackerfoo> Net '$true' is impossible to route within proposed BLK-TL-IOPAD cluster
<hackerfoo> Or rather, how to fix it.
<hackerfoo> Oh, I have to route those through the IOLOGIC sites, I think.
<hackerfoo> I'm just removing them for now.
<litghost> That error was likely complaining that there was no route to the cluster sink to the top level cluster pin
<litghost> But without more details, hard to say
<hackerfoo> I think I fixed that, now I'm at this error: Message: IO block inbuf location was not specified in the pad file.
<litghost> hackerfoo: Not totally certain, but I believe this is something I was warning you about earlier
<litghost> hackerfoo: The placement IO file specifies cluster names, not net names
<litghost> hackerfoo: If there is now more than one net per IO cluster, than the net name may not be equal to the net
<litghost> hackerfoo: Check the ".net" file and see what the cluster names are now
<hackerfoo> Are clusters <block>'s in the .net file?
<litghost> hackerfoo: Let me check
<hackerfoo> I tried changing the IBUF name to "in", but got: ERROR: Re-definition of cell `\in'
<litghost> that's a new one
<hackerfoo> And I can't change in -> inbuf in the .pcf, so how do I change the block name?
<litghost> hackerfoo: I think you need to consume the .net and .pcf and generate the ioplace
<litghost> hackerfoo: e.g. find .pcf constraint in .net, output ioplace for that toplevel cluster
<hackerfoo> Is that prjxray_create_ioplace.py?
<litghost> hackerfoo: Yes
<litghost> hackerfoo: Currently it doesn't consume the .net file, but that was because it didn't need too
<litghost> hackerfoo: Another alturnative is to modify VPR to do the mapping for us
<litghost> hackerfoo: VPR really oaught to be able to constrain toplevel ports at placement locations, rather than by cluster name
<litghost> hackerfoo: But I think it will be faster to parse the .net potentially than updating VPR
<hackerfoo> Yeah. I'm just trying to hack it together for now.