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<_whitenotifier-c> [fpga-tool-perf] acomodi opened issue #125: Refactor and clean up the build system - https://git.io/Jfwzi
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<litghost> ricos: andrewb1999 did the work to add the xc7z020clg400 in https://github.com/SymbiFlow/prjxray/pull/1338 . mithro will have to push a new prjxray-db, which will happen likely this week, maybe sooner
<tpb> Title: Added support for xc7z020clg400-1 and added an openocd config file for pynq-z1 by andrewb1999 · Pull Request #1338 · SymbiFlow/prjxray · GitHub (at github.com)
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<tpb> Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com)
<mithro> @litghost / @timo.callahan: Does that look good?
<tpb> Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com)
<litghost> ricos / andrewb1999: The db push above does not include the xc7z020clg400 changes just yet
<sf-slack> <timo.callahan> litghost: the diffs look good regarding my 100T changes
<sf-slack> <timo.callahan> @mithro rather, the diffs for 100T look good
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<nats`> related topic someone can point me to some documentation about bruteforcing P&R in vivado I'm becoming crazy to meet timing trying by hand all possible "strategy things" :[
<mithro> nats`: Generally you'll have a better time reworking your input code
<nats`> mithro, yep but here it worked pretty well in 2017.4 and don't work anymore in 2019.1 and it's for few hundreds picosecond, by tinkering different mode some it passes sometime it doesn't. I really feel that vivado let you way less control over P&R vs ISE
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<mithro> acomodi: At some point I want to quickly go through the new python modules you made
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<sf-slack> <acomodi> mithro: Sure, for reference, here are the links: https://github.com/SymbiFlow/symbiflow-xc-fasm2bels/pull/2 for fasm2bels and https://github.com/SymbiFlow/symbiflow-rr-graph for the rr_graph
<tpb> Title: Add fasm2bels by acomodi · Pull Request #2 · SymbiFlow/symbiflow-xc-fasm2bels · GitHub (at github.com)
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<sf-slack> <timo.callahan> @mithro, something looks weird in the diffs for the LIOI3_X0Y9. Maybe the diff algorithm got confused. Give me a couple minutes to look at the new raw file.
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<sf-slack> <timo.callahan> @mithro it's fine, the diff display confused me.
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<sf-slack> <timo.callahan> @mkurc: Can you send me a pointer to your scalable multiplier design? That would be very useful! It contains sequential elements (flops), right?
<tpb> Title: symbiflow-arch-defs/tests/9-scalable_proc at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<sf-slack> <timo.callahan> litghost: thx!
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<andrewb1999> acomodi: I got 7020 support working with changes to your zynq-boards branch. What is the best way to go about getting this merged? Do I need to submit a pull request to your repo first or is there some way to submit all these changes to the upstream together?
<litghost> andrewb1999: Open a PR on https://github.com/SymbiFlow/symbiflow-arch-defs
<tpb> Title: GitHub - SymbiFlow/symbiflow-arch-defs: FOSS architecture definitions of FPGA hardware useful for doing PnR device generation. (at github.com)