<mithro>
Raito_Bezarius: The Arty A7 boards (Artix 7) are supported. At some point the Arty Z7 boards (Zynq) should work but nobody has done any testing
<Raito_Bezarius>
mine is indeed Arty S7 (Spartan 7) which seems to have received no support
<Raito_Bezarius>
to be fair, I'd be glad to help around if I can, but unsure how non trivial to help to port symbiflow to this
<mithro>
Raito_Bezarius: The big problem is that the version of Vivado that prjxray uses to document the series 7 bitstream doesn't support Spartan 7 parts and there is one (atleast) vital fuzzer that doesn't work with newer Vivado versions.
<mithro>
timichalak: Project U-Ray uses a new Vivavo version than Project X-Ray, right?
<Raito_Bezarius>
ah I see
<Raito_Bezarius>
what kind of efforts are required to port the vital fuzzer with newer Vivado versions?
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<mithro>
Raito_Bezarius: It's mostly an "unknown" effort type thing -- it definitely isn't super easy
<Raito_Bezarius>
makes sense :D
<mithro>
Raito_Bezarius: The other problem is that fuzzer was written a *long* time ago, so I'm not sure anyone remembers the exact reasons why it doesn't work
<Raito_Bezarius>
what does the fuzzing accomplish exactly? does it helps to discover the undocumented commands that the FPGA uses?
<mithro>
Raito_Bezarius: The entire bitstream of the FPGA is undocumented (it's not like CPUs which generally at least have ISA documentation so you can write a compiler for them....)
<mithro>
Raito_Bezarius: But he never got around to getting the changes upstream and wasn't focused on a working toolchain (rather just verification of security boundaries / features in the FPGA are enabled)
<Raito_Bezarius>
super cool though
<mithro>
Raito_Bezarius: it is unclear to me how much work would be required to get Spartan 7 support into the architecture generation part once prjxray support was finished -- but it /shouldn't/ be a huge amount
<mithro>
Raito_Bezarius: litghost who would probably be the best person to answer is currently on holidays -- some of the antmicro crew like acomodi, mkurc or tmichalak might have some advice
<Raito_Bezarius>
well, I will take note of this and will come back to it once I can allocate time to it, with no real guarantee though as I am not really accustomed to this kind of low level reverse engineering
<Raito_Bezarius>
but I'm curious indeed on the state of this
<Raito_Bezarius>
and what can be done about it
<Raito_Bezarius>
so I might ping litghost in few months again once they are out of holidays (or not) :)
<Raito_Bezarius>
thanks for your many very helpful pointers mithro !
<Raito_Bezarius>
i really appreciate it
<mithro>
Raito_Bezarius: it's actually a lot more massaging of grumpy tools and scripts than anything /really/ complicated
<Raito_Bezarius>
oh :>
<Raito_Bezarius>
that I can do theorically
<Raito_Bezarius>
but does the fuzzing can be destructive?
<Raito_Bezarius>
like can it kill the FPGA?
<mithro>
That is very unlikely (but like all software, no implied guarantee / warranty here) -- the goal is that we never generate a bitstream sequence that Vivado itself wouldn't generate and in fact we do a lot of testing to try and make sure that happens
<Raito_Bezarius>
(to be fair, we have multiple ones so I think I can break at least 2 of them :>)
<mithro>
hansfbaier: Almost all are in various states of bitrot :-)
<hansfbaier>
mithro: Those diagrams are really cool. I am a visual guy mostly for intellectual information. That helps quite a bit.
<mithro>
hansfbaier: I'm a visual person, which is why end up doing the diagrams - Mainly while trying to figure out what the hell something is trying to tell me
<hansfbaier>
mithro: The most difficult thing about getting started is that it is so easy to drown in information (tons and tons of manuals) and it is so hard to see what information is important and which isn't
<mithro>
hansfbaier: Yeap
<hansfbaier>
mithro: The state of things being. I would like to add support for the FPGAs in Litefury and Nitefury, but can't because the database needs to be refactored for deduplication
<hansfbaier>
mithro: Thanks for that link, seems to help. Might have glanced over it.
<mithro>
hansfbaier: I think the db deduplication needs to happen before we wholesale add all Vivado supported Series 7 parts -- if you only care about 1 or 2 parts you can probably just add them...
<hansfbaier>
mithro: The proper way is to deduplicate first, but I have no idea how long it might take and if I could help with it (I have no overview yet where the duplicated information lives)
<mithro>
hansfbaier: Sure, but sometimes it is better to do things the easy way first :-)
<hansfbaier>
mithro: not yet, thanks! I think I only browsed the project x-ray docs, but not the symbiflow documentation, assuming it is self-contained
<hansfbaier>
mithro: Yeah, it sucks to be blocked
<mithro>
hansfbaier: Sometimes it can be useful to understand how something it used to understand why it looks like something
<mithro>
hansfbaier: I would suggest plowing ahead with adding the part which should actually give you a bit of the background needed to understand what needs to be done for the deduplication stuff
<hansfbaier>
mithro: Yes, adding parts seems to be pretty straightforward AFAICT: Add the metadata, run the fuzzers, create pull request. done.
<tpb>
Title: SymbiFlow Environment Providers - Google Drawings (at docs.google.com)
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<hansfbaier>
mithro: I found it really helpful to play a bit with the die-view in vivado/quartus to get a more low level understanding of the FPGAs. Much easier than plowing through the handbooks and much more intuitive
<hansfbaier>
mithro: But that old Vivado version won't concede to upscale to HiDPI, so I configured a hotkey in i3 to switch resolutions
<cr1901_modern>
Okay, essentially the terminology is the same as nextpnr, taking a skim
<cr1901_modern>
Although in nextpnr-land a SLICE _is_ considered a BEL
<hansfbaier>
mithro: what do the NULL/VBRK entries mean? NULL = unknown or unused?
<mithro>
hansfbaier: VBRK means vertical break I think -- I'm afraid I can't recall what that actually means
<mithro>
hansfbaier: I think the NULL tiles are padding in the bitstream to make shift registers and stuff line up? Others might probably know
<mithro>
hansfbaier: I'm don't get to play with all the cool stuff these days, I mostly just do presentations to try and get people funding to do cool stuff
<hansfbaier>
mithro: are the cells of those diagrams individual bits and the rows/columns a factorization of them?
<mithro>
hansfbaier: Something like that, it's explained somewhere...
<mithro>
Heading out, have a good night people
<hansfbaier>
mithro: Good night, thanks!
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<hansfbaier>
crazy, you can get xc7010 boards for $18 including shipping
<_whitenotifier>
[symbiflow-examples] acomodi opened issue #109: Fix counter example - https://git.io/JLwkG
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<_whitenotifier>
[ideas] mark-stopka opened issue #59: Add SymbiFlow tooling to openSUSE - https://git.io/JLrU4