02:45 <_whitenotifier> [fpga-tool-perf] HackerFoo opened issue #303: Can't use --parameters and --run_config at the same time with exaust.py - https://git.io/JLoFO

02:54 <_whitenotifier> [fpga-tool-perf] HackerFoo opened issue #304: Kokoro broke - https://git.io/JLobM

11:49 <hansfbaier> Has anyone tried to reverse the Sipeed Lychee Tang Nano: https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html? Looks like it is really simple, even simpler than the ICE40 FPGAs, and since it is chinese made, probably nobody would complain, if you don´t do clean room.

11:49 <tpb> Title: Sipeed Tang Nano FPGA Board Powered by GW1N-1 FPGA - Seeed Studio (at www.seeedstudio.com)

11:51 <tnt> hansfbaier: https://github.com/YosysHQ/nextpnr/pull/542

11:51 <tnt> https://github.com/YosysHQ/apicula

11:55 <hansfbaier> tnt: Wow, awesome!

13:26 <_whitenotifier> [python-symbiflow-v2x] acomodi opened issue #100: Surelog package generate conflicts - https://git.io/JL6Ml

14:21 <JulianSpeith> hey Dave, I'm working with Nils (greetings btw) on the iPhone bitstream. We're again stuck with the DSP, maybe you have an idea where to look first. For some DSP pins, there is no documentation on which bit is responsible for their signal assignment. This concerns ACCUMCI, ACCUMCO, SIGNEXTIN, and SIGNEXTOUT. For all the other inputs and outputs,

14:21 <JulianSpeith> this table lists the respective signal assignments http://www.clifford.at/icestorm/ultraplus.html.

14:21 <JulianSpeith> any idea what we should have a look at?

14:24 <daveshah> JulianSpeith: hi, those are dedicated signals that connect to an adjacent DSP - there are no config bits related to their routing

20:21 <_whitenotifier> [fpga-tool-perf] HackerFoo opened issue #309: A single JSON file containing all meta.json data would be useful - https://git.io/JLidU