clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mattvenn> I'm looking at parameterising an adc module so it can be a multichannel.
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<mattvenn> this means arrays of inputs and outputs
<mattvenn> verilator validates my module input def, but yosys read_verilog fails
<mattvenn> so just wanted to check that this still holds and I need to follow Cliffords advice in his response
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<ZipCPU> mattvenn: I just tried using 2D arrays yesterday with yosys. It would appear your observation continues to hold.
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<mattvenn> it was reading your blog that inspired me to try and parameterise everything
<mattvenn> what I'm doing instead is using a generate loop to create a set of the modules instead of having the module implement a number of adcs
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<mattvenn> what are you working on?
<mattvenn> Dan?
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