<alnz>
hey everyone. I am working on a project using my own standard cell library and yosys, and just realized that yosys is not using multiple input gates. I am not sure if I am missing a flag or something. As a result of only using two input gates the resulting netlist is really big. Using multiple input gates I think the number of devices in the netlis
<alnz>
t will be significantly reduced. Anybody has seen this before? Any hint/help would be appreciated.
<rqou>
alnz: the "abc" step definitely can use multiple input gates. if you dig around for the "recover_adder" hack you can see an example. otherwise perhaps you can explain more about what you're trying to do?
<alnz>
interesting , just now I am reading about the recover_adder step after techmap ... I will have to try it ..
<alnz>
I am just trying to demonstrate that I can use my own standard cell library to implement relatively complex circuits using yosys. I have been playing with a reduced version of the OR1200.
<rqou>
you probably don't actually want to use recover_adder, but it does manage to invoke abc and get it to use multiple input gates
<rqou>
note that the abc techmapping is not the same as "techmap"
<alnz>
Thanks for the hint ... I am researching it now .. will share my conclusions ...
<rqou>
maybe you can start with the OSU library? i believe that's actually been tested to work (although I've never personally tried it)
<alnz>
Good point .. that can help me eliminate a possible issue with my library ...
<alnz>
ha, just checked the abc log and it reads ... ABC: Library "alnz_ss" from "alnz_ss_sps.lib" has 56 cells (41 skipped: 8 seq; 18 tri-state; 15 no func). ... i guess there is something wrong with my library? ..
<rqou>
possibly a syntax error describing the logic function? sorry the diagnostics here aren't super good
<rqou>
anyways, I have to leave now, so maybe somebody else can help you