clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZipCPU> This is cool ... looks like my article on how to build a wishbone based prefetch hit hacker news.
<shapr> ooh, gotta upvote
<ZipCPU> It was submitted four hours ago, and it's managed to acquire 20 likes so far.
<shapr> I can't immediately see it
<ZipCPU> #29 last I loaded it, "Building a prefetch module"
<ZipCPU> Now it's #30.
<ZipCPU> On the "new" articles page its near #298, since it was submitted 4 hrs ago.
<shapr> upvoted, yay!
<ZipCPU> I now have 21 votes. Thank you!
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<wsm__> hello
<wsm__> I got yosys compiled on mac using a combination of Home
<wsm__> Brew and macports
<wsm__> the make test failed, but that is ok.
<wsm__> the show command fails because fuser does not have an -s option
<wsm__> but show -format ps -viewer gv works
<wsm__> the brew gv fails to run, but a macports gv will work
<wsm__> is there any informational tutorial for mapping to a new device?
<awygle> wsm__: one that Yosys already supports, or one you want to add support for?
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<wsm__> One that I want to add support for
<wsm__> I want to support PSOC5, which has a very small fabric
<wsm__> If you have a tutorial for one that already exists, I can read it, and possibly modify arachne-pr
<wsm__> arachne-pnr
<ZipCPU> wsm__: Hasn't someone already been working on support for the PSOC5?
<wsm__> I am unaware of that
* ZipCPU queries yosys
<wsm__> I do know that psoctools.org
<wsm__> has started determining the bit patterns in the psoc5
<ZipCPU> synth_greenpak4 ... does that have anything to do with PSOCs?
<wsm__> however I am unaware of a PNR for psoc5
<ZipCPU> Yeah ... yosys doesn't provide PNR
* ZipCPU is still searching ...
<ZipCPU> Try this link and see what you find: https://github.com/azonenberg/openfpga/wiki/Cypress-PSoC
<ZipCPU> I know he's been working hard at it, ... I'm just not familiar with how far he's gotten.
<wsm__> yes, I understand that now. However, when I started I did not. I thought yosys did that sort of thing.
<awygle> It's pointfree
<awygle> Iirv
<wsm__> pointfree has been talking to me
<awygle> Don't think we have a PAR or Yosys tech libs
<wsm__> He suggested this channel
<wsm__> OK.
<ZipCPU> Yosys has a "synth_greenpak4" command ... I thought that was for the PSoC, but I've never used it.
<wsm__> based on my searches it is not compatible
<awygle> ZipCPU: synth_greenpak4 is for the silego greenpak 4 series
<ZipCPU> awygle: Are they related at all?
<wsm__> I read some rumbling that they were working on some things for PSOC, but from what I read it was by the GreenPak org an it was proprietary
<wsm__> Thanks for the links. I have some reading to do now.
<awygle> ZipCPU: only in that the efforts are sharing a certain amount of infrastructure and collaboration, iiuc. Certainly pointfree talks about the psoc work in ##openfpga a lot
<awygle> And some of the documentation is on the openfpga wiki
<ZipCPU> Ahh ... okay. Thanks, awygle.
<awygle> Np
<wsm__> thank you. will be reading now......
<wsm__> bye
<wsm__> Quit
<wsm__> :Quit
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<awygle> ZipCPU: in general my understanding is that if there's nothing in https://github.com/cliffordwolf/yosys/tree/master/techlibs for an architecture then Yosys doesn't support it
<ZipCPU> I was just judging from the presence of a "synth_" command for that architecture.
<ZipCPU> Your method is probably better.
<ZipCPU> The exciting new news is that yosys now supports both Altera and Xilinx ... just not the DSP's yet.
<ZipCPU> ... and not P&R either.
<shapr> which xilinx?
<ZipCPU> 7-series.
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<awygle> Yeah, Clifford's tweet earlier was exciting
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