<qu1j0t3>
yeah i guess it has led to a lot of things
<qu1j0t3>
even though i only part way read it.
<qu1j0t3>
i got to the section near the start that said, "here's the math you're going to need:" and then I realised that I didn't even understand Sets properly, so that led me to read about 40 math books ... my process is like the wheels of justice, grinds excruciatingly slow. I'm currently using the same technique to learn analogue electronics ... check back in 15 years ...
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<sorear>
If you think you understand sets, you haven’t
<sorear>
transfinite set theory is *easily* worse than quantum mechanics
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<sensille>
yosys tells me: "ERROR: Unsupported expression on dynamic range select on signal ..." for the line: step[gi] = c_step[stepdir_routing[gi]]; Am i unknowingly using some fancy systemverilog feature here? it works in vivado
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<ZipCPU>
sensille: step[gi] is a single bit?
<ZipCPU>
Are you really sure that's what you want to do, and are you aware of the hardware that will create?
<ZipCPU>
Especially on the ice40, bit selects are expensive.
<sensille>
i want to select a single bit out of c_step, indexed by stepdir_routing[gi]. on xilinx it works as expected in simulation and hardware
<sensille>
the array is small (4), but i want to keep it parameterized
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<qu1j0t3>
sorear | If you think you understand sets, you haven’t // the book doesn't ask for more than naïve set theory
<sorear>
mm, paradoxes
<cr1901_modern>
Question for nextpnr devs... is it considered a bug that the generated chipdbs are placed under "ice40/chipdbs" as opposed to in the build directory?
* cr1901_modern
is doing "spring cleaning" for all the intermediate source files he forgot to clean up b/c the Windows C:\ drive bar is red
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<ZipCPU>
sensille: Consider breaking your code up into two always blocks, either clocked or not.
<ZipCPU>
Be aware, many chips require a whole clock to read from any memories.
<ZipCPU>
cr1901_modern: The chipdb's are a "special" build product. A lot of work has gone into making sure they aren't arbitrarily rebuilt, as well as making sure that they can even be built in the first place.
<cr1901_modern>
Well I deleted them about 20 mins ago, so I guess I'm sitting through 20 mins of waiting next time I rebuild :)
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<sensille>
ZipCPU: my main concern is how to formulate it in a way that yosys accepts it
<daveshah>
sensille: is the complete file somewhere I can have a look at it?
<daveshah>
it means that the array is converted to multiple registers early in the Verilog frontend, rather than to a memory
<sensille>
a memory wouldn't make sense anyway, does it try?
<daveshah>
yes, it normally will for an array, there is a heuristic to stop this in inappropriate cases but it doesn't automatically catch this one for some reason
<ZipCPU>
daveshah: Would it make more sense to declare it as: reg [NCNTRL_BITS_R-1:0][NSTEPDIR-1:0] stepdir_routing?
<daveshah>
ZipCPU: is that valid Verilog?
<daveshah>
looks more like something that SV would have
<ZipCPU>
Good question. I'd have to check if its SV only or Verilog as well.
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<ZipCPU>
daveshah: Looks like you are right. I'm not finding the syntax in Verilog 2005, but I do find it in SV 2012.
<sensille>
daveshah: you replied to my icetime problem, right?
<daveshah>
yeah
<daveshah>
I'm still not sure why the ltout is used at all. but the new icetime should cope with that
<sensille>
i still have a small problem: i rebuilt from git. when i call icetime from the builddir directly, it's fixed. when i just call the one from the path (updated by 'make install'), it still shows that behaviour
<sensille>
do i need to update something else, or is 'make install' not good enough
<sensille>
ZipCPU: timing met, 26MHz :)
<daveshah>
sensille: do a make and make install in icebox too, to update the chipdbs
<sensille>
i did it in the parent, icestorm
<sensille>
testing
<ZipCPU>
Doesn't nextpnr need to be rebuilt if icestorm changes?
<sensille>
no. maybe some paths are mixed
<sensille>
i should uninstall the package and only build from source
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<shapr>
cr1901_modern: did you happen to look at the reduceron and figure out if it'll fit on an ECP5?
<cr1901_modern>
shapr: No, I haven't touched the ECP5 much at all
<shapr>
I'm such an FPGA newbie I don't know what size FPGA I'd need to load a reduceron
<sensille>
i don't even know what a reduceron is :)
<shapr>
sensille: it's a soft CPU designed for executing Haskell and other pure functional programming languages
<shapr>
it's pretty esoteric, so I was amazed cr1901_modern had heard of it :-)
<shapr>
yesterday we had a nifty conversation about this, cr1901_modern said he prefers writing programming languages that have a reasonable mapping to our existing hardware
<shapr>
he's right, the early, easy, naive Haskell compilers produced graph reduction code, which doesn't do well on current imperative hardware
<shapr>
I suspect the recent open source EDA tools effort is related
<shapr>
I'm still angry they didn't dump any of those millions on yosys
<sensille>
daveshah: something funny is going on: if i call just 'icetime ...', it fails. if i call `which icetime` ... it succeeds. if i call 'strace icetime ...' it also succeeds
<sensille>
shapr: thanks, i will read through the links from time to time :)
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<shapr>
sensille: if you poke me sometime when I'm not at work I can send you a much larger pile of links
<sensille>
ok
<shapr>
sensille: talar du svenska eller?
<sensille>
nein
<shapr>
oh well, your name looked Swedish enough :-)
<sensille>
might make it easier to migrate there someday :)
<shapr>
true that
<shapr>
I spent five years there, but I'm from Alabama. My name "Shae Erisson" caused much confusion.
<daveshah>
sensille: have you removed distro icestorm?
<sensille>
daveshah: does icetime something with argv[0]?
<daveshah>
sensille: looks like it is only used in the help message
<sensille>
very strange, but probably something with the shell. now that i've really removed fpga-icestorm, i get the error /usr/bin/icetime: No such file or directory. no nevermind, i'll figure it out
<sensille>
s/no/so/
<daveshah>
icestorm installs in /usr/local
<daveshah>
I wonder if your shell has somehow "cached" the /usr/bin path...
<sensille>
it's a bash. with tcsh i'd just type 'rehash'
<sensille>
hash -r. didn't know bash does that... the funny thing is that 'which' returned the expected path
<sensille>
all good now
<sensille>
shapr: is that just personel interest of you, or are you working at or near something similar?
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<shapr>
sensille: personal interest, my day job is writing voip code in golang
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<shapr>
sensille: what's your day job?
<sensille>
writing low and high level code for a storage hosting platform, and maintaining it
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<awygle>
there's a good bit in the middle explaining how you should treat Larry Ellison the way you treat your lawn mower which i think of frequently
<sensille>
brian (of course) :)
<shapr>
I haven't logged into a Solaris system in a bunch of years.
<shapr>
coworker of mine ported slackware to SPARC
<shapr>
he still has a bunch of hardware
<sensille>
i moved my irc client away from sparc 2 weeks ago :)
<awygle>
i used solaris for like a week in college
<shapr>
My first sysadmin job was a nightmare where I had two weeks of training, after which I was the only sysadmin.
<shapr>
We had SunOS, Solaris, Ultrix, AIX, Irix, Suse, RedHat
<shapr>
and we were a webhost and ISP in Seattle
<sensille>
oh, i know that. i had 6 weeks, and we were 3, and a million customers running on it
<shapr>
My boss, the owner, tried to convince me that I needed to reverse engineer the compiled sendmail configs
<shapr>
That was a nine month long nightmare, but I sure did learn an incredible amount of stuff.
<sensille>
what are "compiled" sendmail configs?
<sensille>
i only ever have written sendmail.cf
<shapr>
sendmail configs go through m4 and output a bunch of regexes
<sensille>
no, of course you write sendmail.cf directy
<shapr>
I didn't know any better :-)
<sensille>
reverse engineering through m4 is a nightmare
<shapr>
I agree
<awygle>
when you say "convinced" are we talking "snipe hunt" convinced?
<shapr>
No, he was serious.
<shapr>
He was between sketchy and flat out shitty.
<shapr>
I got fired because my co-sysadmin deleted /lib on a Solaris box
<shapr>
the owner had sold the install media separately for $1000 or something
<shapr>
I rush ordered a new copy of solaris, and ended up with x86
<shapr>
That was November or something
<shapr>
I never got a W2, so I filed my taxes by including all my pay stubs, the IRS said they couldn't find him either.
* qu1j0t3
used to run sendmail on SunOS
<shapr>
He'd sold off all the SGI / Sun / IBM hardware and skipped the country
<shapr>
A month after I got fired I ran into the sysadmin who'd given me the two weeks training (and told me this was a really bad idea)
<shapr>
He asked who was running the monthly billing perl script
<shapr>
I said "What script?"
<awygle>
LOL
<shapr>
So the company had folded because we hadn't sent out bills for at least nine months.
<qu1j0t3>
holy cow
<qu1j0t3>
i only wish things had changed
<shapr>
We were hosting the Mariners, Yankees, etc. We had a bunch of the largest websites at the time.
<shapr>
I was the only person on call, was often working on two or three hours of sleep
<shapr>
I'd also moved to Seattle for a polyamorous woman ...
<shapr>
Now that I think about it, that story just gets worse the more details I remember.
<shapr>
I thought it'd be easy going from Java programmer to Unix sysadmin
<shapr>
sensille: I like SPARC, it's really cool hardware
<sensille>
haha
<sensille>
a java programmer is not allowed to know the things sysadmins know, otherwise he'd immediately quite doing java
<sensille>
T1 was cool
<awygle>
meanwhile if i have my way i will never sysadmin professionally again
<sensille>
it's maybe 10-20% of my job, that's ok
<sensille>
mainly running the stuff i've built
<qu1j0t3>
awygle: +1
<awygle>
i went from 100% sysadmin to 50% to 10% down to 0%
<shapr>
heck yeah, I don't wanna be a sysadmin again.
<shapr>
facebook keeps asking me to apply to their SRE group, not getting close to that
<sensille>
i love kernel debugging
<sensille>
(but not on linux)
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<qu1j0t3>
shapr: oh, interesting... separated dev/ops seems increasingly antiquated to me
* qu1j0t3
interviewed for google SRE in 2010 and not unhappy about not getting hired
* awygle
as well except 2013
<awygle>
i am a little salty about not getting hired as an SWE in 2017 though just because the interview was such bullshit
<qu1j0t3>
hehe
<qu1j0t3>
i really enjoyed my interviews, but one or two definitely made me feel underprepared.
<qu1j0t3>
"explain how syncookies work."
<qu1j0t3>
i wasn't really looking for an SRE job, SDE was more my interest
<shapr>
friend of mine tried to refer me to google this past weekend, not sure I'm interested
<awygle>
i hate getting, like, riddle questions
<awygle>
not really riddles but just like "let's play this silly algorithm game"
* qu1j0t3
thinks interviewing is plain broken
* qu1j0t3
has spent plenty of time on both sides of the table
<awygle>
"what if we solved a game of hot potato as a closed-form recurrance relation?" "uh i haven't seen a recurrance relation in 10 years" "oh well no job for yout hen"
<shapr>
recurrants
<shapr>
fruit that comes back?
<shapr>
interviewing really is broken
<shapr>
three month work together interview is the best
<shapr>
but has other problems
<sorear>
so my knowledge of useless math trivia could actually be relevant
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<ZipCPU>
Useless math trivia: I spent a semester in college learning how to count. We typically counted fruit in a lunch box.
<shapr>
er, really?
<shapr>
that sounds awesome
<shapr>
fermi estimation?
<shapr>
I've been practicing that, it's way more useful than I ever expected
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<mrsteveman1>
Hey everyone :)
<mrsteveman1>
Am I right to think that I would be limited by BRAM and SRAM sizes long before hitting a limit on the flash available for bitstreams on some of the smaller FPGA boards?
<mrsteveman1>
for example the blackice ii allocates 135KB for bitstreams, out of the 256KB total flash inside the STM32 controller
<ZipCPU>
On the smaller boards, especially the iCE40's, you will be limited by BRAM sizes and LUT counts. There are no DSP's either, so if you need a multiply you'll need to be creative.
<ZipCPU>
Depending on what you wish to do, and the speed you need, the SRAM may or may not be a limitation. Chances are the number of LUTs and lack of multiplies will limit you before then.
<mrsteveman1>
so aside from including initial ram/rom contents inside the bitstream it probably won't matter how much flash is available?
<ZipCPU>
Most FPGA boards have an abundance of flash--leaving plenty for CPU work, if that's what you want to do
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<mrsteveman1>
yea that's what I thought
<mrsteveman1>
thanks :)
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<sorear>
There’s an absolute maximum on the size of a bitstream for every FPGA. I think it’s literally impossible to run out of flash on most boards.