clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<shapr> ok, I have an electronics question, I think
<shapr> I just plugged the i2s pmod https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ into my beaglewire, and I want to run that into a class D amp https://www.adafruit.com/product/1752
<shapr> Do I need to worry about the voltage powering the max9744 amp? should the voltage coming out of the i2s board pins just work regardless?
<shapr> well if I get smoke I'll be sad
<shapr> let's find out
<lutsabound> SMOKE THAT PUPPY!
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<shapr> I'm hoping to steal this: https://github.com/kiran2s/FPGA-Synthesizer
<shapr> I guess I need to read the yosys manual, see if/how timescale works
<awygle> Timescale isn't relevant for synthesis only simulation
<shapr> oh
<shapr> beaglewire has a 100MHz PLL from what I understand
<shapr> reading docs for this i2s pmod say the i2s protocol needs things at a particular speed ...
<shapr> so I have to figure out how to map 100MHz onto whatever speeds i2s needs, right?
<shapr> on the good side, this person added useful comments: https://github.com/kiran2s/FPGA-Synthesizer/blob/master/pmod_out.v#L7
<shapr> it's a 500MHz clock
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<awygle> Yep
<awygle> You can see in that code the mapping from a 500mhz clock to a 2000 kHz clock and some others
<shapr> oh?
<shapr> I don't think I have an easy input pmod handy
<shapr> oh wait
<awygle> Check out MCLK in that code you linked
<shapr> I have http://adafru.it/419 handy
<awygle> SCLK and LRCLK likewise
<shapr> but I'd have to check the pinout to see if it's pmod compatible
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<shapr> I have the amp hooked up to the out part
<shapr> port*
<shapr> and it looks like this verilog source was written for this exact pmod, hurrah!
<shapr> I'd like to hack this into a demo that just plays tones, hmm
<shapr> ok, I think this will work if I 1. fix the clocks and 2. remap the pins
<shapr> awygle: is there a collection of verilog recipes?
* shapr reads the clock code again
<awygle> uhh not really. that's an interesting idea
* awygle writes that down
<shapr> heh, it helped me pick up several programming languages
<awygle> I shouldn't say no, there might be. I just don't know where.
<shapr> fair enough
<shapr> I was asked yesterday where to find beginner crochet/knitting videos, but I've been doing that so long I wouldn't know
<awygle> Also I only just this moment woke up enough to realize this was #Yosys and not ##fpga
<shapr> I understand
<shapr> I can move the conversation?
<awygle> Na it's cool
<awygle> I was just napping
<shapr> ok
<shapr> I thought you could only do things as often as the clock in an FPGA?
<shapr> if the incoming clock is 500MHz, how do you scale that up to 2000...
<shapr> oh waittt
<shapr> KILO hertz
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<shapr> I'd guess that the ~ operator in verilog is invert the bits in that register?
<shapr> assuming that's correct, why is that used as part of a counter from 500MHz to 2MHz?
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