clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<cr1901_modern> mwk: The -icells param you mentioned to read_verilog works for my needs for now. I don't have the time to look deeply into this right now, but I _feel like_ the backends that use attrmvcp aren't using it properly.
<cr1901_modern> When I run them, all src/loc attributes on all nets are moved to cells b/c of the "n:*" selection tacked on at the end
<cr1901_modern> When I thought the point was to move src/loc from ports to the cells
<cr1901_modern> err, move the attributes on the verilog modules ports to the cells driving/driven by the verilog module ports*
<mwk> ... my gut feeling is that they should not be doing that anyway
<mwk> hmm
<cr1901_modern> What I'm using: attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]
<cr1901_modern> for example- this works (both the wire _and_ the cell have to be in the selection)
<cr1901_modern> fwiw, those attrmvcps in synth_greenpak/coolrunner have always been this way. Makes me wonder if it's syntax changed over time, or a typo was copied
<mwk> ... or someone just didn't care
<cr1901_modern> who knows :). I wanted to do the "use attributes for placement and io_type" trick b/c I thought it'd be easier to prototype.
<cr1901_modern> But the time it took me to get it working- among other real life things this week- I could've used ECP5's LPF parser for this
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