clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<Raito_Bezarius> I'm trying to formal verify a simple block RAM design by using (* anyconst *) and I'm getting the error: "base: ERROR: Failed to get a constant init value for \f_data: $memrd$̊am$./memory/block_ram.sv:72$1572982_DATA" unsure if I'm doing something wrong or what's the way forward from there
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<Raito_Bezarius> FWIW, there is a: " initial f_data = ram[f_addr];
<Raito_Bezarius> line in my fdesign
<Raito_Bezarius> ram is afaik initialized and f_addr is a (* anyconst *) address
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<Raito_Bezarius> okay, maybe putting initial assume (f_data == ram[f_addr]); looks better
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