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cyrozap >
azonenberg: "... s6 is kinda the winME of xilinx"
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cyrozap >
azonenberg: How so?
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pie_ >
any of you ever use simulink for fpga stuff?
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rqou >
achievement(?) get: mainlanders all think i'm from HK and HK people all think i'm from the mainland :P
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ZipCPU >
pie_: Nope!
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azonenberg >
cyrozap: s6 was the architecture that was so bad none of the next-gen parts reused anything from it
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azonenberg >
all of 7 series is based on the virtex architecture
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cr1901_modern >
And s3 was considered good?
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cr1901_modern >
azonenberg: Doesn't 7 reuse the LUT arch from 6?
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azonenberg >
No, it reused the arch from v6
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azonenberg >
s6 was a cut down v6 that had a bunch of stupid things in it
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azonenberg >
cr1901_modern: s3 was like win98, old but pretty decent for what it was
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azonenberg >
Which would make v6 win2k, then 7 series XP (where they unified all of the designs and just had high/low end variants)
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cr1901_modern >
where's ME?
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awygle >
azonenberg: do you have a 'roadmap' in mind of architectures to work on?
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balrog >
azonenberg: what makes s6 that bad?
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azonenberg >
balrog: no carry chains in some slices (7 series has them everywhere which makes it much more useful for arithmetic-heavy logic)
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azonenberg >
limited routing resources
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azonenberg >
awkward holes in the routing around the GTPs
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qu1j0t3 >
WeRateFPGAs
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cr1901_modern >
The WeRateX is getting old
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lain >
our secret is actually WeHateFPGAs
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cr1901_modern >
I think it's WeHateFPGAToolchains
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cr1901_modern >
'cept the FOSS one because
*shock* it's not unpleasant to use
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azonenberg >
This is not an FPGA. This is a bowl of weirdly colored spaghetti.
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cr1901_modern >
Well, the CPU is routed in mostly one place :D
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lain >
azonenberg: lol
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azonenberg >
lain: Things i want my par to do better
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nextGEN31 >
Good evening everyone I'm looking for info about the piracy of android or apple, the cloning of telephone this kind of info, I'm in the right place
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