03:54 <azonenberg> At some point i should optimize my characterization

03:54 <azonenberg> right now i am using one bitstream per measurement

03:54 <azonenberg> so i spend a LOT of time downloading bitfiles and comparatively little collecting data

04:02 <openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHgFz

04:02 <openfpga-github> openfpga/master 13ed97b Andrew Zonenberg: Now characterizing IOBs and cross-connectors and saving delay values in the object. Still no serialization

04:02 <azonenberg> also, http://thanatos.virtual.antikernel.net/unlisted/greenpak-characterization-09.png

04:03 <azonenberg> Where'd nats go? havent seen him in a while

04:33 <openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHgbm

04:33 <openfpga-github> openfpga/master dfd9ea1 Andrew Zonenberg: Now measuring I/O buffer delays across voltage corners (for 3.3V nominal range only)

04:34 <azonenberg> http://thanatos.virtual.antikernel.net/unlisted/greenpak-characterization-12.png voltage corner measurements

04:34 <azonenberg> only 3.3V range, i need level shifters to do other stuff

04:41 <azonenberg> http://thanatos.virtual.antikernel.net/unlisted/greenpak-characterization-14.png

04:41 <azonenberg> here's a plot

07:14 <azonenberg> aaand now i can serialize process corners, but not actual timing numbers, to JSON

07:14 <openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHgpB

07:14 <openfpga-github> openfpga/master 6079494 Andrew Zonenberg: Initial work on timing data serialization

07:14 <azonenberg> that's it for tonight

08:03 <openfpga-github> openfpga/master 57950d4 Andrew Zonenberg: Finished saving IOB data to JSON

08:03 <openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHgho