<carl0s>
nats`, yeah they are not good enough, but why do you say that?
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
lexano has quit [Ping timeout: 255 seconds]
digshadow1 has joined ##openfpga
digshadow has quit [Ping timeout: 268 seconds]
promach_ has joined ##openfpga
azonenberg_work has quit [Ping timeout: 264 seconds]
eduardo_ has joined ##openfpga
eduardo__ has quit [Ping timeout: 255 seconds]
azonenberg_work has joined ##openfpga
promach_ has quit [Remote host closed the connection]
promach_ has joined ##openfpga
digshadow1 has quit [Ping timeout: 276 seconds]
promach_ has quit [Read error: Connection reset by peer]
promach_ has joined ##openfpga
promach_ has quit [Remote host closed the connection]
carl0s has quit [Quit: Leaving]
azonenberg_work has quit [Ping timeout: 255 seconds]
m_t has joined ##openfpga
Bike has quit [Quit: fd]
m_t has quit [Quit: Leaving]
pie_ has joined ##openfpga
scrts has quit [Ping timeout: 260 seconds]
scrts has joined ##openfpga
pie_ has quit [Ping timeout: 276 seconds]
<whitequark>
azonenberg: oh god
<whitequark>
I just learned how PCH-based Intel chipsets implement GbE
<whitequark>
PCH has the GbE core and there's a PHY outside. PCH communicates with PHY over what is a PCIe interface electrically
<whitequark>
... except it runs at half the rate (1.25 GT/s) and it transmits bare Ethernet packets
<rqou>
oh yeah, i knew that
<rqou>
it's pretty hacky
<cyrozap>
"Hey, should we use an SGMII core for the GbE on the PCH?" "Nah, we'd either have to license one or write it from scratch. Just copy/paste one of the PCI-e cores, that'll probably work."
<whitequark>
cyrozap: it's not as easy
<whitequark>
PCH has 26 "HSIO" lanes and it can mux its peripherals all over them
<whitequark>
there are five different ones where GbE can be mapped, for example
<whitequark>
almost everyone is PCIe or USB capable
fpgacraft1_ has joined ##openfpga
fpgacraft1 has quit [Quit: ZNC 1.7.x-git-709-1bb0199 - http://znc.in]
fpgacraft1_ is now known as fpgacraft1
pie_ has joined ##openfpga
pie_ has quit [Ping timeout: 240 seconds]
lexano has joined ##openfpga
digshadow has joined ##openfpga
pie_ has joined ##openfpga
Bike has joined ##openfpga
pie_ has quit [Ping timeout: 240 seconds]
pie_ has joined ##openfpga
pie_ has quit [Read error: Connection reset by peer]
pie_ has joined ##openfpga
pie_ has quit [Ping timeout: 255 seconds]
scrts has quit [Ping timeout: 276 seconds]
azonenberg has quit [Read error: Connection reset by peer]
scrts has joined ##openfpga
openfpga-bb has quit [Ping timeout: 258 seconds]
azonenberg_work has joined ##openfpga
digshadow has quit [Ping timeout: 240 seconds]
azonenberg_work has quit [Ping timeout: 260 seconds]
amclain has joined ##openfpga
m_t has joined ##openfpga
<mtp>
hi whitequark
m_w has joined ##openfpga
pie_ has joined ##openfpga
azonenberg_work has joined ##openfpga
digshadow has joined ##openfpga
scrts has quit [Ping timeout: 255 seconds]
scrts has joined ##openfpga
<whitequark>
hi mtp
<mtp>
how goes
<mtp>
i mean, besides the clusterfuck of horrors you're dredging up from the Intel architecture manuals
<lain>
you should see the NDA shit
<lain>
it's a comedy of errors ove rhere
<balrog>
no wonder it's NDA
<mtp>
i have a couple yellow-book intel manuals
<mtp>
from, like, 2003
<lain>
https://i.imgur.com/tEvm5zb.png I love when they update documents without bumping the revision. I almost didn't notice there was a new version.
<lain>
their document management system is some dude in a corner office I think
<lain>
I feel sorry for whoever it is, because they're clearly overworked
<balrog>
"removed RAID mode" hah
<balrog>
probably because it was broken
<lain>
likely, yeah
<mtp>
RAID mode: full of BUGS
<lain>
I won't say what chip that's for but it's very new, I'm not even sure if it's generally available yet. it's been interesting working with such a new chip, you get to watch as they rip out all the features that don't actually work lol
<lain>
the way it seems to work is they put everything into the chip, then periodically they'll say "X is no longer POR", where POR is intelspeak for Plan Of Record, meaning it's on the chip but it's either broken or is not being tested in production so use at your own risk
<lain>
once it hits general release, a good chunk of the features have been removed, and the remaining features will be vaguely indicated as to which are "tested" and which are not tested on an ongoing basis
<lain>
as best I can tell, "tested" means "a big customer is using this so we won't break it."
<lain>
:P
<whitequark>
mtp: ehh still alive i guess
<whitequark>
lain: lol
<lain>
I haven't dug into xeon docs yet but they seem to be a lot better :P
<davidc__>
heh; have you seen some of their BGA layouts?
<davidc__>
that stuff is insane
<davidc__>
(Also, re: intel docs/support. Its dramatic the difference in support you receive depending on your email suffix. using username@smallstartup.com gets no response. using usernamealias@megacorpthatboughtstartup.com - immediate response)
<lain>
hah
<lain>
yeah it usually takes a week to get a response out of my contacts, and then they just pass it on to someone else and it disappears into the intel management telephone game
<davidc__>
it was amazing how fast their turnaround was for the @megacorp
<lain>
for the outer balls - inner are larger balls, different pitch (die shadow area)
<davidc__>
(to be fair, this just involved them losing a datasheet in a website reorg, so it was probably all within their web org, rather than engineering)
<lain>
ahh
<davidc__>
lain: yeah, those packages make me think drugs were involved
<davidc__>
lain: or field-solver-guided-package-optimization, which is equivalent
<lain>
davidc__: they have some docs on stuff like strain relief and whatnot, but it's not like I understand the mechanisms well enough to say if that's puffery or not :P
<lain>
the only reason I have an NDA is because I whined a bunch on the embedded design center forums
<davidc__>
lain: once upon a time I saw a talk video where they talked about optimizing ball placement for SI using a field solver
<lain>
oh jeez
<lain>
that seems ... :|
<lain>
I'm surprised I got intel to agree to let me open-source my entire design
<davidc__>
lain: which design is that?
<lain>
davidc__: it's a tinysmol laptop / handheld computer, originally I was going for something a little larger but now I'm looking at this sort of form factor: http://www.larwe.com/technical/img/hpc_a_11a.jpg
<lain>
a lil bigger, 5.5" amoled captouch 1920x1080 is the screen I'm eyeing right now
<lain>
if it ever gets finished the goal is to sell the mainboard, possibly with a little enclosure, as a SBC... and maybe the full handheld if somebody wants to pay for it, but that bit is mostly for myself and a few friends so it'll be $$$ to fab lol
<davidc__>
gotcha
<lain>
if I can sell enough to cover my costs I'll be happy, but it's mostly a personal project
<lain>
attaching an fpga to the soc via pcie x2 for hardware hackery, sorta like bunnie's novena laptop
<lain>
8GB lpddr3, 64GB eMMC
<lain>
4x usb type-c ports, 2 of which have displayport alternate function, 1 is dual-role, and the other has sata alternate function (no, sata alt func isn't a real thing, I'm just hooking 2 sata ports up to the usb3 mux then making my own cable with 2x sata+power connectors)
<lain>
usb type-c does seem awesome for esata replacement though. everything's rated for sata electrical layer, and you can fit 2 sata ports _and power_ in one type-c connector
<lain>
</ramble>
<mtp>
man
<mtp>
if i had infinite time/energy, i'd sit down with a bale of weed and a breadboard and make a 68040-based SBC and a forth
<mtp>
unfortunately, capitalism requires me to sell my body and mind for survival
<lain>
haha
<davidc__>
mtp: what, is the bale for a table for the breadboard? That doesn't make much sense.
<davidc__>
There's probably cheaper supporting structures out there.
<davidc__>
Seems unnecessarily complicated.
<mtp>
the bale is for me
<lain>
lol
<davidc__>
mtp: ... there are better chairs too.
<mtp>
at the right level, all of the shitty decision paralysis my mind would otherwise have, just melts away
<whitequark>
'a bale of weed'
<whitequark>
is there a nuke inside? :P
<qu1j0t3>
haha
<qu1j0t3>
mtp: SBCs, eh. This is relevant to my interests. I got some 68000s last year for a buck each.
<qu1j0t3>
mtp: and a couple of free 6805's via cctalk list. I can tell you who to ask if you want one of those.
<mtp>
qu1j0t3, i don't have the time/energy to actually do this
<qu1j0t3>
mtp: sorry to hear this
<qu1j0t3>
mtp: let me know if i can help tho
<mtp>
pay me 150k$/yr to fuck around
* qu1j0t3
wishes he could
digshadow has quit [Quit: Leaving.]
<ZipCPU>
qu1j0t3: Have you looked at any of the CPU emulators on OpenCores?
<qu1j0t3>
briefly. i know that's an option.
<qu1j0t3>
i think building a physical SBC will teach me other things though.
<ZipCPU>
Quite true.
digshadow has joined ##openfpga
<eduardo_>
ZipCPU: did you publish the QSPI Flash reader somewhere? Would be cool to have a Flash reader for icoboard with PMOD Hardware.
digshadow has quit [Ping timeout: 240 seconds]
scrts has quit [Ping timeout: 240 seconds]
Hootch has quit [Read error: Connection reset by peer]
scrts has joined ##openfpga
<ZipCPU>
eduardo_: Yes, although I haven't validated whether or not it works on the ICO board yet (I was trying to get there last night ...)
<ZipCPU>
That's the one I'd use if I was in a logic constrained environment.
<ZipCPU>
eduardo_: Doesn't clifford's stuff give you full access to all of the hardware? I guess I had just assumed so, and so hadn't put as much of a priority on it as I would've otherwise.
digshadow has joined ##openfpga
<azonenberg_work>
Soooo
<azonenberg_work>
There is a good chance that i may end up spending a decent amount of time on coolrunner stuff over the summer
<azonenberg_work>
basically finishing my research that was incomplete after recon '15
<rqou>
um, right i was also supposed to have been working on that :P
<rqou>
right now i finally got so sick of c++ i'm porting my vhdl parser code to Rust
<rqou>
and with some tips from <housemate>, it might actually be faster due to better cache locality
<rqou>
it's definitely probably more correct because i'm pretty sure i managed to C++ footgun myself and not notice
<eduardo_>
ZipCPU: ?? Clifford did a single SPI implementation for the weight scale for 33C3, but no QSPI and no Flash. He is currently mainly into formal verification and not very much into Verilog projects or icoSoC.
<eduardo_>
The last thing he did was the HyperRAM (which was really a PITA). The new icoBoards will all come with 64MBit Hyperram and 8 MBit SRAM.
<ZipCPU>
eduardo_: Ok ... but I didn't think the ICO board had a QSPI flash.
<ZipCPU>
I think I see my mistake now ... the S25FL127S calls itself a SPI flash memory, but internally it supports dual and quad spi modes. Ok. Let me check if the schematic supports it.
<ZipCPU>
I'm not sure how I would command a Quad SPI mode through the Mach chip.
<ZipCPU>
That leaves you stuck with SPI mode.
<ZipCPU>
I suppose you might manage to program dual SPI through the Mach chip ... but it might take some work.
<ZipCPU>
Still ... my plan was to put together a SPI controller for the ICO. The controller is built, but not my test infrastructure.
<ZipCPU>
As a result, while I can build it for the part, I have no way of testing that it works (yet).
digshadow has quit [Quit: Leaving.]
m_w has quit [Quit: leaving]
m_t has quit [Quit: Leaving]
<ZipCPU>
eduardo_: Will you be building a new board? This time with QSPI flash, and a UART?
laintoo_ has joined ##openfpga
Finnpixel|2 has joined ##openfpga
laintoo has quit [Ping timeout: 240 seconds]
Finnpixel has quit [Ping timeout: 240 seconds]
laintoo_ is now known as laintoo
pie_ has quit [Quit: Leaving]
azonenberg_work has quit [Ping timeout: 276 seconds]
Zarutian has joined ##openfpga
Zarutian has quit [Read error: Connection reset by peer]