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<rqou>
dumb question: how do i know if the ice40 pll is locked properly?
<rqou>
ah, there's a LOCK signal
<felix_>
rqou: have you seen that the 34c3 will be in leipzig this year and that the venue will be bigger, so getting tickets probably won't be a problem this year
<rqou>
i did see the leipzig announcement (in German only?)
<felix_>
i payed about 380 euros for a double room for 5 nights, which is maybe 12 minutes away by foot, so 38 euros per person per night
<jn__>
>The start of presale is going to be announced at CCC’s events blog at https://events.ccc.de/.
<felix_>
if you book some hostel room, it might cost half of that or even less, but since i'm no longer student, i just threw a bit more money at that ;)
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<felix_>
but i booked the hotel room (nh hotel) before the official announcement, so it might be more expensive or even fully booked now
<rqou>
azonenberg_work: your UART works on ice40 btw
<rqou>
(once you actually open the correct USB port :P )
<rqou>
yosys gets really upset about your // synthesis translate_off hot comments though
<azonenberg_work>
rqou: yes i know
<azonenberg_work>
i'm refactoring the uart to deal with some of that stuff
<azonenberg_work>
it's in the queue waiting for a rewrite/cleanup
<azonenberg_work>
But not there yet
<rqou>
but the important part is that it does work
<azonenberg_work>
Yeah
<azonenberg_work>
The rewrite will likely not change the synthesis at all
<azonenberg_work>
just restructuring of the code to be cleaner
<azonenberg_work>
do the oversampling with a loop instead of writing it by hand
<azonenberg_work>
etc
<rqou>
eh, right now i'm just doing a hack so I don't care that much
<rqou>
it's not even set up for simulation right now; it's all YOLO-based debugging :P
<azonenberg_work>
yeah i know
<azonenberg_work>
but i'm trying to make a more stable IP library
<azonenberg_work>
rqou: also did you see my tweet earlier about the starshipraider host board?
<rqou>
i did
<rqou>
nice
<azonenberg_work>
final design is ready for tapeout as soon as i get home from work unless anyone has anything to tweak
<rqou>
why doesn't ODT work btw?
<azonenberg_work>
7 series HR bank input termination is either split or 100 ohm differential
<azonenberg_work>
TMDS/CML needs 50 ohm on each leg to 3V3
<azonenberg_work>
which is not an available ODT topology
<rqou>
ah ok
<azonenberg_work>
and i didnt have the pcb space for it
<azonenberg_work>
so i'm changing the intereface
<azonenberg_work>
i'm now using LVDS instead of CML as the RX signaling
<azonenberg_work>
LVDS doesn't need a termination voltage, it uses 100 ohm differential across the pair
<azonenberg_work>
7 series can ODT this iff VCCO=2.5V
<azonenberg_work>
i had that bank at 3.3
<azonenberg_work>
and couldn't chaneg it to 2.5 b/c i needed LVCMOS33 outputs
<azonenberg_work>
But i didnt have space for vias so a termination voltage was a no-go
<azonenberg_work>
a discrete resistor across the diff pair, otoh, totally fit
<azonenberg_work>
so i just put 0201 passives across the pairs
<azonenberg_work>
problem solved
<azonenberg_work>
In the final board, i will most likely have a FGG676 part
<azonenberg_work>
with one bank driven at 2V5 for ODT'd LVDS inputs
<azonenberg_work>
and another driven at 3V3 for LVCMOS33 outputs
<azonenberg_work>
but in FTG256 i only had four banks, i needed two for ram at 1.8V and one for ethernet and flash at 1.8V
<azonenberg_work>
only had one more bank and so that had to be 3.3
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