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rqou>
wow, yosys doesn't warn at all if it infers a latch
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rqou>
wow, and now i footgunned myself by assigning the same bit pattern to multiple FSM states
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rqou>
yeah, it's really bad that the only sign you created a latch is icetime telling you your timing estimate is "1000006.48 ns"
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openfpga-github>
yosys/master bd4ed19 Clifford Wolf: Add first draft of simple C back-end
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openfpga-github>
yosys/master 241dc7d Clifford Wolf: Update ABC to hg rev e79576e10d72
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openfpga-github>
yosys/master 1a4b7c6 Clifford Wolf: Fix boolector support in yosys-smtbmc
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