<azonenberg> For really fine pitch stuff like 0201 and 01005 passives
<azonenberg> or plucking bond wires etc
<azonenberg> dont have the model number handy but they were 10 x 50 micron points
<azonenberg> i pretty much only use them at 30x or higher magnification under the microscope
<m_w> nice
<azonenberg> they were like $50 a pair
<azonenberg> but totally worth the money
<m_w> I do all of my work without magnification :)
<azonenberg> If you can do 0201s without mag
<azonenberg> or inspect placement on a 0.35mm pitch WLCSP
<azonenberg> i'm *very* impressd
<azonenberg> :p
<m_w> I don't usually go that small
<azonenberg> i usually dont either
<azonenberg> but mag is never a bad thing
<m_w> azonenberg: how long did the assembly take? it looks like a pretty high part count
<azonenberg> Photo of the board with no components is dated 18:06
<azonenberg> at 21:17 i was done with the bottom and about to reflow the second side
<azonenberg> 21:57 i had finished reflow, soldered the PTH components, and verified correct PSU voltages
<azonenberg> So, call it a touch shy of 4 hours?
<m_w> not too bad
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<azonenberg> OOOk so
<azonenberg> finally
<azonenberg> I am able to measure delays between pins on my fpga board to ~78 ps precision
<azonenberg> It seems pretty consistent
<azonenberg> Right now it only uses two specific pins, i'll work on calibrating out pcb delay next
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<azonenberg> I have 12.734 ns round trip time, including PCB trace and I/O buffer delays, when looping a pin back to itself
<azonenberg> well, shorting out to in with two 0.1" headers
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<pie_> of all things, i thought port forwarding would be easy
<azonenberg> lol
<pie_> ffs
<pie_> it worked before
<pie_> openwrt pls
<pie_> azonenberg, nice
<pie_> and idk how to iptables so i cant even figure out whats wrong with this junk that used to work
<azonenberg> getting some funny results, have to debug a little bit more....
<azonenberg> idk if its just that some of my cheap jumpers have high resistance or if i'm screwing up crunching the data somewhere
<azonenberg> Once i have the ability to do 3-point delay measurements (driving or sampling from any of 3 pins)
<azonenberg> then i'll be able to calibrate pcb/io buffer delays out
<azonenberg> Right now i can only measure round trip delays, which is a little bit limiting
<azonenberg> With only 2 points there's no way to know delay for each leg independently
<azonenberg> but with 3, if you can measure A-B A-C B-C
<azonenberg> some basic algebra will give you the length of each leg
<azonenberg> At that point i can characterize the pcb trace delays on the greenpak devkit
<azonenberg> and start measuring true pin-to-pin delays
<pie_> im sorry but can anyone help me with this dumb networking crap ive been staring out of my head for hours cluelessly
<rqou> pie_: i can try to help
<rqou> what's up?
<pie_> yeah sorry this is bs but i have no idea why its not working and im not familiar with iptables
<rqou> i'm reasonably familiar with iptables
<rqou> what are you trying to do?
<pie_> so ive got openwrt, and im trying to forward a port (it doesnt really matter because none of them seem to work)
<pie_> *doesnt matter which
<pie_> everyhting works fne on the lan, but no wan access, and its not the isp blocking the port
<rqou> ugh you have tcpmss
<pie_> i cant connect to ports on the wan ip on a shell on the router
<pie_> if that helps with anything
<rqou> tcpmss is terrible
<pie_> yeah i need to update my openwrt
<pie_> idk if that will do anything about that
<rqou> nah, it's fine to leave that
<pie_> uh hold on my wan ip and my wan ip are different...
* pie_ scratches head
<pie_> dynamic dns gives me one ip and ifconfig on the router gives another
<pie_> dydns is ccorrect though
<pie_> might be pppoe stuff
<pie_> ok sorry i have no idea, just disregard the last few stuff i said
<pie_> i dont know if its even an iptables problem though, it shouldnt be
<rqou> yeah, your iptables looks right
<pie_> ugh
<rqou> have you tried running packet traces to see if any packets arrive at the .203 machine?
<rqou> or this that a windows box?
<pie_> when i try to connect to the external ip?
<pie_> well i guess i could try
<pie_> but re: everything works on the lan
<rqou> afaik lan won't ever use the nat path
<pie_> and routing tables should make it not traverse to wan right?
<pie_> yeah
<pie_> on that note...hm
<rqou> actually wait
<rqou> it _does_ work on the lan
<pie_> well there is a "nat loopback" option so this should still work
<rqou> ?
<pie_> yes
<rqou> that actually doesn't work by default
<pie_> i mean
<pie_> sorry you misunderstood
<pie_> it works on my lan ip
<pie_> so i can connect to 192.168.1.whatever
<pie_> but not through the router ip or dns
<pie_> (but im pretty sure that used to wor)
<rqou> if you are trying to access the service on the public IP when you are on the same network, you need NAT loopback/hairpin enabled
<mtp> oh
<pie_> yeah i do have that enabled (afaict)
<pie_> but good to know
<pie_> i only found out what that is 10 minutes ago
<rqou> i don't see rules in your iptables dump for that
<pie_> well theres a box thats checked in the openwrt ui >.>
<pie_> ok ive got my hands on a host that can scan me externally and its not open either way
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<pie_> tcpdump alludes to nothing going in or out with respect ot that port
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<pie_> trying to connect from a rempote host shows no reply on the remote host and no incoming on the local host
<openfpga-github> [yosys] azonenberg pushed 3 new commits to master: https://git.io/vHWWz
<openfpga-github> yosys/master 05df3db Clifford Wolf: Add "setundef -anyseq"
<openfpga-github> yosys/master 9ed4c9d Clifford Wolf: Improve write_aiger handling of unconnected nets and constants
<openfpga-github> yosys/master d9201b8 Clifford Wolf: Change default smt2 solver to yices (Yices 2 has switched its license to GPL)
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<azonenberg> wooopwoop
<azonenberg> I'm starting to get useful data
<azonenberg> Just fiddling around right now, no automation
<azonenberg> but at this point i can measure cross connection 11 as being ~80 ps slower than cross connection 1
<azonenberg> for my specific die, at 3.3V, at my ambient temp
<azonenberg> At some point i'm going to make a big pile of bitstreams to do measurements better
<azonenberg> and script this up
<azonenberg> Ooh, LUT0 in1 -> out is 310 ps slower than in0
<pie_> inb4 not even the manufacturer has this data
<azonenberg> They don't
<azonenberg> I'm doing propagation delay for now just playing around
<azonenberg> but will be measuring setup/hold shortly
<pie_> xilinx are noobs
<azonenberg> They do not characterize setup/hold
<azonenberg> this isnt xilinx
<azonenberg> this is asileg
<azonenberg> silego*
<pie_> xilinx are still noobs
<pie_> :P
<azonenberg> i'm using an artix on the other end as my test signal generator
<azonenberg> Doing this properly will require automation
<azonenberg> testing across a range of Vdd values
<azonenberg> testing across a range of ambient temps
<azonenberg> etc
<azonenberg> i'm doing it by hand just to kinda get a feel for how to measure things
<azonenberg> But this is gonna be good data
<azonenberg> like, knowing which lut pins are slower than others means that the optimizer may be able to re-order lut inputs to improve timing
<azonenberg> if one path isnt critical and the other is
<azonenberg> rqou: my measurement is sensitive enough to see a 240 ps lag through pin 3 vs pins 4 and 5
<azonenberg> which, interestingly enough, is the pin that i reworked
<azonenberg> no idea if this is coincidental (the wire on the devkit happens to be longer) or my rework has a slightly higher resistance than the original wire
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<pie_> sure
<pie_> why this specific device btw?
<azonenberg> Because the vendor does not have a static timing analyzer
<pie_> ah
<azonenberg> I figured it'd be educational to characterize the device myself and write one
<azonenberg> i already have a mostly completed HDL flow
<azonenberg> but no STA
<azonenberg> the vendor datasheet has typical propagation delays for rising vs falling
<azonenberg> but not setup/hold times
<azonenberg> or any info on PTV corner
<azonenberg> s
<azonenberg> just typical delays
<azonenberg> I plan to characterize multiple dies at upper and lower voltage extremes
<azonenberg> and a range of temperatures
<azonenberg> to provide full cross-PTV timing data
<pie_> vnice
<azonenberg> wow, THIS is interesting
<azonenberg> i'm measuring LUT3_0 in2 as 3.28 ns to output
<azonenberg> but in0, in1 are 7.89, 8.05
<azonenberg> Smells wrong but i havent found anything up with my data yet
<pie_> swap the polarity!~one!?#!
<azonenberg> like, the in0 to in1 propagation delay is about what i expected
<azonenberg> but in2 being massively faster smells wrong
<azonenberg> 4.61 ns is a lot
<azonenberg> Let's see if it holds for another lut3
<azonenberg> Nope
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<azonenberg> LUT3_1 doesn't do the same
<azonenberg> lol
<azonenberg> it acts as i'd expect
<azonenberg> but LUT3_0 is funky