<openfpga-github>
yosys/master 9ed4c9d Clifford Wolf: Improve write_aiger handling of unconnected nets and constants
<openfpga-github>
yosys/master d9201b8 Clifford Wolf: Change default smt2 solver to yices (Yices 2 has switched its license to GPL)
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<azonenberg>
wooopwoop
<azonenberg>
I'm starting to get useful data
<azonenberg>
Just fiddling around right now, no automation
<azonenberg>
but at this point i can measure cross connection 11 as being ~80 ps slower than cross connection 1
<azonenberg>
for my specific die, at 3.3V, at my ambient temp
<azonenberg>
At some point i'm going to make a big pile of bitstreams to do measurements better
<azonenberg>
and script this up
<azonenberg>
Ooh, LUT0 in1 -> out is 310 ps slower than in0
<pie_>
inb4 not even the manufacturer has this data
<azonenberg>
They don't
<azonenberg>
I'm doing propagation delay for now just playing around
<azonenberg>
but will be measuring setup/hold shortly
<pie_>
xilinx are noobs
<azonenberg>
They do not characterize setup/hold
<azonenberg>
this isnt xilinx
<azonenberg>
this is asileg
<azonenberg>
silego*
<pie_>
xilinx are still noobs
<pie_>
:P
<azonenberg>
i'm using an artix on the other end as my test signal generator
<azonenberg>
Doing this properly will require automation
<azonenberg>
testing across a range of Vdd values
<azonenberg>
testing across a range of ambient temps
<azonenberg>
etc
<azonenberg>
i'm doing it by hand just to kinda get a feel for how to measure things
<azonenberg>
But this is gonna be good data
<azonenberg>
like, knowing which lut pins are slower than others means that the optimizer may be able to re-order lut inputs to improve timing
<azonenberg>
if one path isnt critical and the other is
<azonenberg>
rqou: my measurement is sensitive enough to see a 240 ps lag through pin 3 vs pins 4 and 5
<azonenberg>
which, interestingly enough, is the pin that i reworked
<azonenberg>
no idea if this is coincidental (the wire on the devkit happens to be longer) or my rework has a slightly higher resistance than the original wire
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<pie_>
sure
<pie_>
why this specific device btw?
<azonenberg>
Because the vendor does not have a static timing analyzer
<pie_>
ah
<azonenberg>
I figured it'd be educational to characterize the device myself and write one
<azonenberg>
i already have a mostly completed HDL flow
<azonenberg>
but no STA
<azonenberg>
the vendor datasheet has typical propagation delays for rising vs falling
<azonenberg>
but not setup/hold times
<azonenberg>
or any info on PTV corner
<azonenberg>
s
<azonenberg>
just typical delays
<azonenberg>
I plan to characterize multiple dies at upper and lower voltage extremes
<azonenberg>
and a range of temperatures
<azonenberg>
to provide full cross-PTV timing data
<pie_>
vnice
<azonenberg>
wow, THIS is interesting
<azonenberg>
i'm measuring LUT3_0 in2 as 3.28 ns to output
<azonenberg>
but in0, in1 are 7.89, 8.05
<azonenberg>
Smells wrong but i havent found anything up with my data yet
<pie_>
swap the polarity!~one!?#!
<azonenberg>
like, the in0 to in1 propagation delay is about what i expected
<azonenberg>
but in2 being massively faster smells wrong
<azonenberg>
4.61 ns is a lot
<azonenberg>
Let's see if it holds for another lut3