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<azonenberg> So, i'm now working on a simulation bridge
<azonenberg> from ISim to libjtaghal
<azonenberg> that exposes the verilog simulation of the CPLD as a libjtaghal-compatible socket server
<rqou> wtf why isim?
<azonenberg> rqou: because this is more portable
<azonenberg> VPI works with iverilog and nothing else i have
<azonenberg> I'm writing a portable bridge that just uses pipes and $fread()/$fwrite()
<azonenberg> So it works with isim
<rqou> only on *nix though
<azonenberg> i've done this before for co-simulation over real jtag to real FPGA
<azonenberg> Correct
<azonenberg> But this is intended to be used for me to bring up my emulator
<azonenberg> it's not a public-use tool
<azonenberg> i mean it'll be foss licensed and in the repo but it's not meant for general consumption
<azonenberg> it's literally a shim that makes a verilog simulation look like an actual jtag dongle to a libjtaghal-compatible app
<azonenberg> (for lulz, i should try and make a bridge that speaks the xilinx cable daemon protocol too, so i can have impact jtag isim :D
<rqou> or you can get diamondman to plug the xilinx cable protocol into his jtag abstraction?
<azonenberg> jtaghal is a jtag abstrction
<azonenberg> i'm not sure why he's not using it
<azonenberg> it's a fairly clean layered model and should be pretty portable (not that i've tried)
<azonenberg> and i already have a jtag server that can bridge any jtaghal-compatible endpoint to a TCP socket
<azonenberg> so basically what i'm going to do is implement a jtaghal adapter class that talks to a pipe using some simple ascii protocol
<azonenberg> and use my existing jtagd to host it
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<pervo> azonenberg, yo
<balrog> I think he wants something that does more
<balrog> (re: jtaghal)
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<azonenberg_work> o/ pervo
<azonenberg_work> balrog: what do you mean?
<balrog> azonenberg_work: I don't know, I couldn't get a clear anser :/
<balrog> answer*
<azonenberg_work> pervo: so you're trying to push state from a cycle-accurate emulator of an FPGA design into the actual FPGA?
<azonenberg_work> is it full techmap-accurate (i.e. exact same RAM topologies, no register balancing, etc)?
<azonenberg_work> or, say, shift reg luts vs dffs etc
<azonenberg_work> because if not, you're going to have a *hell* of a time doing the mapping
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