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<azonenberg> whitequark: also as a FYI
<azonenberg> i played with my peltier more, took it out to 3.5A (single stage)
<azonenberg> Got it from 25C down to -16C
<azonenberg> So a 41C gradient
<azonenberg> (measured with an IR thermometer on the surface of the plate)
<azonenberg> With a second stage i should have no trouble at all hitting -40
<Zorix> stacked?
<azonenberg> Yes
<azonenberg> just gonna stack two of this same unit
<azonenberg> i have a second one on order
<azonenberg> but i wanted to see how far i could push this one first
<Zorix> neat idea, never considered that as a possibility
<azonenberg> its a pretty standard technique for large gradients
<Zorix> i have thought about playing with one for the reverse thermoelectric properties
<azonenberg> As a thermocouple you mean?
<azonenberg> My interest is in characterizing greenpak devices across the full operating temperature/voltage range
<Zorix> yep
<Zorix> ah
<azonenberg> So i need to be able to get a tiny (2x3 mm, few mW heat output) chip
<azonenberg> from ambient up to +85 or down to -40
<azonenberg> And a few points in between
<Zorix> yea peltier is best for that
<Zorix> but each chip isnt the same, so your testing is not going to be the same for all of them, they will differ somewhat
<azonenberg> You mean each die, or each peltier?
<azonenberg> My test breakout is a board with one greenpak and one I2C thermal sensor, that will both be in contact with the peltier to do closed-loop feedback control
<Zorix> each die in this case..
<azonenberg> That is the point :p
<azonenberg> i'm going to be testing a few dozen samples from several different wafer lots
<Zorix> ah so you are individually rating them
<azonenberg> Not exactly
<azonenberg> i mean i am collecting data on single dies
<azonenberg> But the goal is to find min/max process corners
<azonenberg> So i can say, for any un-tested die
<azonenberg> its performance is likely to be somewhere in this range
<azonenberg> I'll try to do some statistical magic to add a safety margin for extreme tolerance variations beyond the samples i've tested
<Zorix> have to go with the worst of each extreme to know what the safe tolerances are going to be
<azonenberg> but as a minimum i'll be testing several samples from wafer lots 5P501 and P6001
<azonenberg> at -40C, +85C, and a few points in between
<azonenberg> at 1.8 +/- 5%, 3.3 +/- 10%, and 5V +/- 10%
<azonenberg> every die at all temp/voltage conditions
<Zorix> have a specific application in mind?
<azonenberg> then plot both the spread and min/max
<azonenberg> Writing a static timing analyzer :p
<Zorix> ah
<azonenberg> Hard to do that without setup/hold/propagation delays
<azonenberg> The vendor only publishes typical delay at 1.8, 3.3, 5V
<azonenberg> not min/max
<azonenberg> and no setup/hold
<azonenberg> So i'm fixing this :p
<Zorix> nice hehe
<azonenberg> Once i have the setup done, it should be fairly easy to port to other devices
<azonenberg> I need to optimize my measurement setup, it takes way too long to measure a single die right now
<Zorix> how many are you going to measure?
<azonenberg> Depends on how big the spread i see is
<Zorix> it could change with each lot
<azonenberg> this is a sample spread for one metric across five dies, constant voltage/corner
<azonenberg> I have samples from two wafer lots and unfortunately didn't pay attention to which lot each die was from when i made that plot
<azonenberg> conjecture: 4 and 1 are same lot, 0,3,2 are the other
<azonenberg> Vendor is working on getting me samples from a third lot as well
<azonenberg> I'll test multiple dies from each lot as well to quantify variation within a lot
<Zorix> seems to be all within about 2ms
<azonenberg> This is raw data before compensating for io buffer delay etc
<azonenberg> which i've measured individually
<Zorix> ah
<azonenberg> The point is more, i can quantify the delay
<azonenberg> also pretty sure that's ns, not ms
<Zorix> ah yes ns
<Zorix> i was zoomed out and it was hard to tell
<azonenberg> There's some fun linear algebra going on to compute point to point delays from path total delays
<azonenberg> i may have to land a probe on the die and measure input and output buffer delay separately
<azonenberg> thats one of the big unknowns that i am guesstimating right now
<azonenberg> I have access to a SEM/FIB with probes at $WORK
<azonenberg> So i am totally willing to do this if needed :p
<Zorix> very cool
<Zorix> dont get those kinds of fun toys at my job
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<azonenberg> Soooo let's see, greenpak stuff is still kinda on hold pending the peltier and characterization boards
<azonenberg> Coolrunner emulator has some really funky bugs that i wasnt able to figure out tonight
<azonenberg> i think i'm going to script up a bit of stuff then try to implement simulation mode
<azonenberg> see if i can get visibility i'm not getting on the devkit
<azonenberg> The big thing i have to do is figure out how to load a jed into the ram via simulation
<azonenberg> What i may do is implement a virtual jtag TAP that talks to isim over a pipe or something equally derpy
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<pie__> you know whats cool?
<pie__> phased arrays
<azonenberg> They are indeed
<azonenberg> whitequark: ^
<jn__> missing dollar inserted
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<whitequark> azonenberg: oh my god
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<pie__> im slightly confused
<lain> pie__: glad I'm not the only one
<cr1901_modern> I think it's a bunch of LaTeX crap
<cr1901_modern> Oh yea, jn__'s comment gives it away
<cr1901_modern> https://mastodon.social/@cr1901/11495908 Person who comments first with the correct answer gets a virtual cookie
<jn__> i don't have a mastodon/*social account, but that & should be an |
<lain> the & should be a |
<jn__> timing :D
<lain> :D
* cr1901_modern throws out virtual cookies for all
<cr1901_modern> I didn't notice it for a week T_T
<cr1901_modern> (on and off)
<jn__> i've spent a few weeks on a bare metal project where i loaded a few megabytes of signed code on one processor, and used it on a different processor which isn't cache-coherent with the first one
<jn__> the signature check always failed and i didn't know why. turns out i had to flush the cache first
<pie__> sure i figured latex but i dont really get it
<rqou> overfull hbox is some kind of error that latex likes to give
<rqou> i don't know what it actually means though
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<pie__> ok so basically the joke is that the stuff looks a lot like a latex "rendering" log?
<pie__> (which is what i figured i guess)
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<qu1j0t3> rqou: it means that it couldn't fit the contents of a horizontal "box" to the desired width, within the prevailign tolerances. Most commonly a line of a justified paragraph. (and often caused by a long word that can't be hyphenated in a good place)
<qu1j0t3> it's much like a compiler warning; you can then go and reword or insert discretionary breaks or take other manual action to resolve.
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