<rqou>
ugh wtf am i doing why haven't i done anything useful this week
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<whitequark>
debian?
<rqou>
what about debian?
<whitequark>
too many copies of the C++ runtime
<rqou>
nah, debian isn't that bad
<whitequark>
well sort of, it's not really runtime
<rqou>
i was thinking Windows
<whitequark>
of the C++ compiletime
<rqou>
every version of Visual Studio comes with a new version of the c runtime
<rqou>
and every time your program wants to open a file or print or whatever, a bunch of other people's code (and the corresponding c runtimes) get injected into your process
<whitequark>
the last one comes with some sort of facade shite
<whitequark>
that's nearly impossible to use if your use case is slightly different
<whitequark>
libucrt etc
<rqou>
afaik ucrt is better
<whitequark>
hypothetically
<whitequark>
if you need to like, integrate code written in ocaml
<whitequark>
it's even worse
<rqou>
why?
<whitequark>
some sort of undocumented relocation in libucrt
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<rqou>
hmm, never heard about this problem
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<rqou>
whitequark: ok, i searched a bit about your ocaml problem
<rqou>
yeah, static linking is busted, but afaik it always was?
<whitequark>
no?
<rqou>
er, it always could be
<rqou>
*could have been
<rqou>
the point of ucrt as i understand it was to stabilize the abi of the DLL runtime
<whitequark>
it doesn't matter if the CRT ABI is stable if it's statically linked
<rqou>
right
<rqou>
afaik it's recommended not to do that on windows
<rqou>
although it does work, unlike glibc
<whitequark>
microsoft killed that with ucrt initially
<whitequark>
then half of their isvs started complaining
<whitequark>
and they had to restore it
<rqou>
in general the windows platform is still a giant mess though
<rqou>
i love how random shit gets loaded into my process so that the user can pick a file to open
<rqou>
and then some of these shitty libraries break things in hilarious ways by e.g. changing the locale or the floating point control word
<azonenberg>
Global state in general is a nightmare
<azonenberg>
:p
<awygle>
do commercial FPGA tools do placement based on wirelength or timing?
<rqou>
project: try to figure out how to duct-tape together wirelength and timing :P
<azonenberg>
They're timing driven, to some extent
<azonenberg>
But it would not surprise me if they use wire length for the inner loop
<azonenberg>
then tweak based on timing
<azonenberg>
as wire length is probably a lot faster to compute
<awygle>
a lot of these academic papers use pure wire length for placement, then have a timing-driven router
<rqou>
yeah
<awygle>
then again, a lot of these algorithms are also evaluated by saying "the size of the FPGA i'd have to invent to run my results is smaller than the size of the FPGA you'd have to invent to run your results", so...
<azonenberg>
lol
<azonenberg>
yeah i really want open tools for real fpgas to allow this research to move better
<azonenberg>
in fact
<azonenberg>
being able to back-annotate all the way to synthesis would be nice too
<azonenberg>
some optimizations like register retiming, for example, would benefit from knowing routing delays based on congestion and placement constraints
<awygle>
i am excited about algorithms right now, i've been retrofitting some of these papers onto arachne-pnr, but i don't feel that i know enough about FPGAs to properly genericize things
<azonenberg>
Well, glad to have you aboard :)
<azonenberg>
I'm probably busy this weekend, and traveling for defcon most of next week, but we should definitely meet up and discuss things when i get back
<rqou>
i'm headed to defcon
<azonenberg>
openfpga defcon meetup? Who else is going
<awygle>
sure, i'll be in the throes of moving probably but i'm sure i'll find some time
<azonenberg>
defparam: you gonna be there? iirc you came last year
<awygle>
speaking of, my new company has offered to send me to a few conferences each year, anything in particular i should put on my list if i'm trying to get into the fpga communities?
<azonenberg>
I havent been to any FPGA cons
<azonenberg>
$DAYJOB is infosec
<azonenberg>
So the overlap is things like bitstream reversing
<azonenberg>
Which is usually at security/RE cons
<awygle>
sure
<awygle>
okay, my brain is bouncing off flowcharts. until tomorrow, everybody
<cyrozap>
Not sure if we were already aware of this or not. It isn't listed on our wiki, at least.
<rqou>
oh yeah, we (at least azonenberg and I) are aware of this
<rqou>
the wiki is a mess
<cyrozap>
Also jhol (from that link you posted) is really good at commit messages :P
<cyrozap>
Seriously, it pains me when I see a Git repo and all the commits are either "commit" or "new code" or "WIP" or really any other entirely unhelpful message.
<rqou>
i sometimes do that for personal projects
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<azonenberg>
pie_: gonna guess that board doesnt have stuff for inner layer rework on it
<azonenberg>
is it even functional?
<pie_>
i have not the faintest clue
<pie_>
but its from pace so it cant be bad right? :PPP
<awygle>
rqou: jhol and i discussed that in #yosys a bit the other day. he seems to share the general feeling that vtr/vpr is overly academic and hard to do real things with
<azonenberg>
awygle: I think it's something to learn from
<azonenberg>
Not something to use
<awygle>
azonenberg: agreed
<azonenberg>
I think we should write a new PAR tool designed for scalability and parallelism from the start
<azonenberg>
Something that can scale to an ultrascale+ part, while not having excessive overhead for an ice40 when run on 1-4 cores
<azonenberg>
awygle: do you have access to the openfpga wiki yet?
<azonenberg>
First step will be a literature survey of what's out there
<azonenberg>
Collect a bunch of links to papers and your comments on them
<awygle>
i do not
<azonenberg>
What's your github nick?
<azonenberg>
awygle?
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<awygle>
yes
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