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<awygle> azonenberg: pretty sure i'd have to take the ferry and *then* drive the Mercer corridor. nooooo thanks :P
<mtp> ick
<mtp> i used to live in Renton, that sucked, i can't imagine the Bremerton side of the water
* awygle currently lives in renton
<mtp> it's impossible to have a social life unless you have a car and are willing to sit in traffic
<mtp> that's my big gripe of renton
<awygle> yeah i'm moving to redmond probably next week sometime. although after my commute home today i want to sign a lease and move in tonight
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<azonenberg> mtp: see, i just have no social life outside work and IRC :p
<azonenberg> and i have a bike and outrun traffic routinely
<azonenberg> also i pretty much completely avoid king county outside of work
<azonenberg> we spend all our time in kitsap
<azonenberg> Ooook so, fingers crossed i will actually have some time to do research tonight
<azonenberg> Gonna try and port my logic analyzer core to work over a uart so i can use it on no-NoC systems
<azonenberg> which will help me debug some issues i've been having in the greenpak timing core
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<awygle> is there an easy way to visualize a blif?
<rqou> load it into yosys and run "show"
<awygle> oo really?
<rqou> yes
<rqou> but in general, "is there an easy way to visualize a <foo>" is "get rekt"
<awygle> dope
<rqou> more visualizers would be pretty nice
<rqou> azonenberg's "IDA for hardware?" :P
<rqou> i have no idea what the UI for that would be though
<awygle> "la la la let's visualize this graphOHJEZUS" wow that's ugly
<rqou> feel free to write a better one :P
<jn__> see you in five years ;P
<rqou> while you're at it, please implement this: https://github.com/azonenberg/openfpga/issues/91
<awygle> lol sorry, not a graphics dude by any means
<awygle> maybe someday i'll write a force-directed blif viewer to learn d3
<awygle> in this case i actually meant that the circuit was ugly
<rqou> gephi is pretty neat, except it's java
<rqou> it accepts .dot files
<azonenberg> rqou: my initial implementation is going to just be a straight decompiler with no ui
<azonenberg> just bit -> v
<azonenberg> we'll see what i have time for after that
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<cyrozap> I am now the proud owner of two working Digilent Nexys 4 DDR boards :)
<cyrozap> Total cost: $150 shipped
<jn__> nice
<cyrozap> The USB port on one of them had bad solder joints (stupid micro USB), but that was an easy fix.
<rqou> hope there aren't any blown io pins
<cyrozap> The best part about that austion was, it was obvious the seller had no idea what they were selling, since it was in a lot of a bunch of chipKIT boards, some PMODs, an HS2, and _one DDR2 DIMM_.
<cyrozap> The worst part was that they shipped all the stuff in a box WITH NO PADDING WTFFFFFFF
<cyrozap> It was just plastic bags :P
<cyrozap> s/austion/auction/
<cyrozap> rqou: The preloaded demo bitstream (!) runs without any issues on both boards, so I'm thinking they're ok, and that they were probably never used :/
<rqou> could be used in a lab
<rqou> i'm pretty sure berkeley's boards never had the demo bitstream erased
<rqou> it was always using sram programming
<cyrozap> Oh, interesting, I hadn't considered that.
<cyrozap> I guess I'll just have to boundary-scan the thing to check all the IOs, but as I said it seems fine.
<cyrozap> So yeah, aside from the few bent pins and having to rework the USB port, I'm pretty satisfied with my purchase. Now I finally have some 7-series chips to play with, and they're XC7A100T's, too!
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<azonenberg> cyrozap: :)
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<azonenberg> Welp
<azonenberg> looks like i'm gonna have to fix some Splash stuff regarding include paths
<azonenberg> yay, my favorite
<azonenberg> more yak hair
<rqou> azonenberg: going to defcon?
<azonenberg> Yep
<rqou> when are you travelling?
<azonenberg> Thursday early afternoon
<azonenberg> Will have a throwaway phone, PM me tomorrow and i'll give you the number
<rqou> wow, that's late
<azonenberg> just bought it and havent set it up yet
<rqou> i should be road-tripping tomorrow
<azonenberg> rqou: i reeeally do not want to reimplement a whole C preprocessor to do dependency scanning
<azonenberg> but gcc's dep scanner has some really annoying quirks that are breaking splash / requiring painful workarounds
<azonenberg> tl;dr depending on a lot of complex factors i don't understand
<azonenberg> the list of dependencies may include absolute paths
<azonenberg> relative paths to your project dir
<azonenberg> and relative paths to directories in the -I list
<azonenberg> So trying to turn a filename with no context into an absolute path is nontrivial
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<pie_> rqou, ugh im stuck on a JS parser bug
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<pointfree> "The Magic of a Via-Configurable Regular Fabric" http://iccd.et.tudelft.nl/Proceedings/2004/22310338.pdf
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<azonenberg> pointfree: my first problem with the paper
<azonenberg> unless i'm missing something grossly obvious
<azonenberg> it doesn't say what process they targeted
<azonenberg> ah nvm
<azonenberg> 180 nm, but no specifics
<pointfree> So far I have found two companies providing via configured (ASIC's): eASIC and Triad Semi https://www.triadsemi.com/ http://www.easic.com/ ...are there others?
<azonenberg> easic is the main one i was familiar with
<pointfree> another one: "An Integrated Design Flow for a Via-Configurable Gate Array" http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.87.4621&rep=rep1&type=pdf
<pointfree> I don't see any mention of "one-time programmable in either paper" I would love to get some sort of devkit for a via configurable device. I hope I'm wrong but it seems triadsemi and easic have a different definition of low cost.
<lain> low cost relative to a set of N masks
<lain> iirc like 8 years ago easic had 45nm for $45k setup cost
<lain> that's crazy cheap :P
<azonenberg> for a 45nm asic, heck yeah