<azonenberg>
mkk: As of now we have Yosys inference support for GreenPAK shift registers and counters in a subset of modes, there's a few odd modes of the counters that you have to do explicit primitive instantiation for
<azonenberg>
But that shouldn't be that hard to fix if someone wanted to commit the time
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<cr1901_modern>
balrog: Remember when FPGAs were feasible to mine BTC? And remember a time when more than half the total circulation wasn't owned by like 5 ppl running an "ASIC farm"?
* cr1901_modern
doesn't, but...
<balrog>
cr1901_modern: yeahhh......
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<rqou>
i mean, i have very little stake in what happens to BTC
<rqou>
i put $50 into BTC around 2015
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<rqou>
er, azonenberg: yosys IL is incapable of representing all features in coolrunner-ii
<rqou>
specifically dual-edge FFs
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<azonenberg>
rqou: Hmmm
<azonenberg>
Flag those as an error and fail to translate them for now
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<azonenberg>
we should talk to clifford about it
<rqou>
yeah, i've already filed an issue for yosys to gain support for those
<rqou>
afaict adding the basic support to handle both posedge and negedge in a process should be simple enough, but a lot of other stuff in yosys cares about FFs
<rqou>
latches will be very very fun too
<rqou>
because yosys and xc2 have different priorities for set/reset/latch-enable
<azonenberg>
you may have to synthesize it into logic that explicitly prioritizes
<azonenberg>
if both S and R are hooked up
<rqou>
yeah
<rqou>
we should verify this on hardware
<rqou>
want to start speculating how the macrocell is physically built?
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<azonenberg>
I'd rather just RE it
<azonenberg>
when i have time :p
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<rqou>
what about your CSCI 4974/6974 homework 1?
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<azonenberg>
that was the IO cell iirc
<azonenberg>
and i dont think anyone fully figured it out
<rqou>
should have started with something simpler and more drama-ful like VRC7 :P
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<rqou>
ugh i just spent $120 on two replacement mice because both of mine are broken
<rqou>
just hardware things
<azonenberg>
Ok having a serious WTF with my logic analyzer
<azonenberg>
it looks like the null at the end of the string, and the width byte after it, are trading places
<azonenberg>
for example pll_reg_addr should be 0x 72 00 05 00
<azonenberg>
instead if have 72 05 00 00
<azonenberg>
WTFF
<azonenberg>
Even more interesting, it's like this when i look at the synthesized ro min vivado
<azonenberg>
So my code that shuffles this around into a bram is borked?
<rqou>
what is this?
<azonenberg>
This is the symbol table of my logic analyzer
<rqou>
why does the LA have a symbol table?
<azonenberg>
So you don't have to manually type group 512 1-bit channels into named buses
<azonenberg>
every time you reconnect
<azonenberg>
The LA symbol table includes a unique name to identify this LA, the width/depth of the capture, the frequency of the capture clock, then name/width (and soon data type) of all of the fields
<azonenberg>
But my code to shuffle it into a block ram is apparently borking
<rqou>
arrgh why does yosys always seem to maliciously apply postel's law?
<azonenberg>
what's that again?
<rqou>
read_json on "{}" is accepted
<rqou>
"Be conservative in what you do, be liberal in what you accept from others"
<azonenberg>
lol
<azonenberg>
i mean to be fair that is liberal...
<azonenberg>
yosys needs better error reporting, i wont deny that :p
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<mtp>
but json.parse("{}") is an empty json object
<rqou>
right, and then yosys promptly goes and creates no new modules
<mtp>
not exactly seeing the problem here, you're passing in a container containing nothing and it's doing nothing
<azonenberg>
Symbol table was built with buggy Vivado, activating workaround for ROM scrambling
<azonenberg>
15037 is 00 00 3A BD
<azonenberg>
then 512 is 00 00 02 00
<azonenberg>
then 64 is 00 00 00 40
<azonenberg>
so somehow one zero byte moved from the start to the end of the buffer??
<azonenberg>
Or something like that
<rqou>
always remember: not as buggy as pic16/18 compilers :P :P
<azonenberg>
i didnt even think it was possible to have a synthesis tool that can't evaluate a ROM correctly
<azonenberg>
it's consistently, but with no discernable logic, moving bytes in my rom around
<azonenberg>
it almost seems like it's doing an endianness swap somewhere???
<azonenberg>
but it isnt applying it to strings
<azonenberg>
only other stuff
<azonenberg>
welp
<azonenberg>
I now have a functional enoguh logic analyzer to debug the rest of this board :p
* azonenberg
goes off to bed
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<awygle>
rqou: speaking of yosys rtlil, is that what your vhdl parser emits/is intended to emit?
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<rqou>
awygle: no, it's intended to hook into the AST layer (which is a layer above)
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<rqou>
azonenberg: thanks to a browser crash, i noticed that your openfpga-dashboard.antikernel.net cert is expired
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<rqou>
plz fix
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<rqou>
oh dang azonenberg_work you're actually in the office today? :P
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<azonenberg_work>
rqou: lol yes
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<azonenberg_work>
also WTF xilinx
<azonenberg_work>
it's maxing out four cores of my laptop
<azonenberg_work>
... to *download* vivado
<azonenberg_work>
at 5 MB/s
<rqou>
gotta send a lot of ACKs
<rqou>
:P
<azonenberg_work>
the downloader is written in java, lol
<azonenberg_work>
How do you even DO this?
<rqou>
i don't recall having to use this
<rqou>
i thought i just used a plain http downloader?
<rqou>
oh btw: your openfpga-dashboard.antikernel.net cert is expired
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<azonenberg_work>
I'm using their new web installer b/c the alternatiev is to download a 20+ GB package containing windows and linux binaries and all of the devices i cant use in webpack
<azonenberg_work>
PM my main nick and i'll look into it when i get home
<rqou>
yeah i already did
<azonenberg_work>
Actually
<azonenberg_work>
Poke whitequark
<azonenberg_work>
That VM should be set up to auto-renew with letsencrypt
<azonenberg_work>
If it failed, that's a problem
<rqou>
hmm, looking at crt.sh, a renewal did happen
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<rqou>
somebody didn't SIGHUP something
<azonenberg_work>
Oh
<azonenberg_work>
So it renewed but the server has to reset since it has the old cert cached?
<azonenberg_work>
I can log into the VM when i get home (dont have creds on this box) to restart it
<rqou>
usually SIGHUP tells the server to reload that
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<whitequark>
azonenberg_work: oh
<whitequark>
yeah that could be
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<azonenberg_work>
whitequark: do you have ssh access to reload or do i have to do it after work?
<azonenberg_work>
i forget
<whitequark>
I do
<azonenberg_work>
Ok
<azonenberg_work>
Let me know when you get it fixed, or if you have trouble
<whitequark>
azonenberg_work: fixed
<azonenberg_work>
Did you root-cause it? Can you keep it from happening again?
<rqou>
confirming it works here
<whitequark>
azonenberg_work: a deficiency in my config maintenance scripts
<whitequark>
I've presumably fixed it elsewhere but it didn't work the previous time a rotation should have happened
<whitequark>
once I definitely fix it I'll also apply the fix to your VM
<whitequark>
elsewhere meaning whitequark.ogr
<azonenberg_work>
.ogr? Is that like a TLD for ogres and trolls? :p
<whitequark>
.org*
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<rqou>
ugh, i finally have to fix the "feature" where xc2bit doesn't know where the global nets are
<rqou>
:P
<azonenberg_work>
Lol
<rqou>
as in, it does know what bits control the global nets
<rqou>
but it doesn't know which FB or macrocell it is on
<azonenberg_work>
But it is trying to figure out what FB they're from
<azonenberg_work>
fun fun
<rqou>
i just need to read the datasheet and hardcode the numbers
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<qu1j0t3>
.ogr, nice
<qu1j0t3>
finally a useful tld
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<azonenberg_work>
rqou etc: Anyone want to verify this for me?
<azonenberg_work>
in particular, try building that verilog on a couple of tools
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<azonenberg_work>
Verify you get the "expected" result anywhere but vivado
<awygle_m>
Good lord I have got to find an acceptable android irc client
<rqou>
i normally use androirc
<azonenberg_work>
awygle_m: s/find/write/
<azonenberg_work>
:p
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<awygle_m>
I have really bad thrash problems with that. I think I just need to move my quassel core to linode or something.. Seems to be an android client
<awygle_m>
rqou: so you're trying to create an AST from VHDL that's compatible with the AST that Yosys spits out from verilog?
<rqou>
not strictly
<rqou>
i'm probably going to need to extend the Yosys AST
<rqou>
but right now it's nowhere close to that
<awygle_m>
Any particular reason not to target the IL?
<rqou>
i wanted to share the logic that breaks down processes
<rqou>
and the logic that breaks down if/else-if into muxes
<awygle_m>
Hmm interesting
<awygle_m>
azonenberg: did you have a chance to look at any of my notes on papers etc? Such as they are?
<azonenberg_work>
awygle_m: Skimmed them briefly
<awygle_m>
Planning to spend all day Sunday working on that project
<azonenberg_work>
We should have a meetup at some point to discuss in more detail
<azonenberg_work>
Preliminary thoughts: GPUs are a pain in the butt and we will still need multi-node parallelism
<azonenberg_work>
I would focus on scaling to multiple nodes using an analytic placer
<azonenberg_work>
Then we can always parallelize within nodes using a GPU down the road
<azonenberg_work>
I don't like annealing, it scales poorly
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<pointfree>
Stay tuned for the pi-dsi + portpin tabulations, coming up soon! (pi-dsi to miscellaneous on-chip peripheral mappings might take somewhat longer to sort out)
<pointfree>
cyrozap: What's the deal with your psoc to verilog parser? I'm interested.