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<openfpga-github>
[yosys] rqou pushed 5 new commits to master: https://git.io/v5lfi
<openfpga-github>
yosys/master 5a2031f Robert Ou: coolrunner2: Initial fixes for special p-terms...
<openfpga-github>
yosys/master 66b255c Robert Ou: coolrunner2: Fix mapping of flip-flops
<openfpga-github>
yosys/master afd096c Robert Ou: coolrunner2: Combine some for loops together
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<openfpga-github>
[yosys] azonenberg pushed 3 new commits to master: https://git.io/v5lJD
<openfpga-github>
yosys/master 52e5078 Andrew Zonenberg: Merge branch 'master' of github.com:azonenberg/yosys
<openfpga-github>
yosys/master a475a66 Andrew Zonenberg: Fixed duplicate declaration in GP_COUNT8_ADV model
<openfpga-github>
yosys/master 9c1ad0f Andrew Zonenberg: Added missing makefile entry for extract_counter (lost during merging?)
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<openfpga-github>
[yosys] azonenberg pushed 1 new commit to master: https://git.io/v5lIr
<openfpga-github>
yosys/master 9591afc Andrew Zonenberg: extract_counter: Added optimizations to remove unused high-order bits
<openfpga-github>
[yosys] azonenberg pushed 2 new commits to counter-extraction: https://git.io/v5lID
<openfpga-github>
yosys/counter-extraction 16043b7 Andrew Zonenberg: Merge branch 'counter-extraction' of github.com:azonenberg/yosys into counter-extraction
<openfpga-github>
yosys/counter-extraction ed1e3ed Andrew Zonenberg: extract_counter: Added optimizations to remove unused high-order bits
<azonenberg_work>
Lol, 20% of the open issues in yosys and 60% of the open pull requests are from me
* azonenberg_work
wonders if this classifies him as an active user
<rqou>
i wonder why more people don't use yosys
<azonenberg_work>
Good question
<rqou>
sure, it's pretty limited with "advanced" HDL constructs, but it's design is so KISS and understandable
<azonenberg_work>
i also want to file a ticket for process handling improvements, if not more than one
<azonenberg_work>
thats a big one for me, it's bit me several times
<rqou>
oh yeah, that part is super dumb right now
<azonenberg_work>
in particular bad handling of multiple consecutive nonblocking assignments in an always block
<azonenberg_work>
But i want to test more exhaustively and explicitly enumerate each of the ways it fails
<rqou>
i was thinking the pattern matching to figure out what type of FF you wanted
<azonenberg_work>
and file a ticket for each
<azonenberg_work>
Oh actually i think i have another one
<azonenberg_work>
Inferring latches when it doesn't need to
<azonenberg_work>
in particular the GP_DCMP simulation model
<rqou>
oh yeah yosys latch support is awful in general
<azonenberg_work>
it has a case(reg[1:0])
<azonenberg_work>
with cases for 0,1,2,3
<azonenberg_work>
in a combinatorial block
<azonenberg_work>
but since there's no default it infers a latch
<azonenberg_work>
i want to test this more to be certain then file a ticket
<rqou>
wait of course
<rqou>
you forgot about x/z :P
<azonenberg_work>
srsly?
<rqou>
i think you need the full_case parallel_case thingy
<azonenberg_work>
i've never seen a synth tool do this if you handled all 1/0 cases
<azonenberg_work>
for synthesis x and z dont exist
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<rqou>
wait then what's the point of full_case parallel_case? (other than to cause synth/sim mismatches)
<azonenberg_work>
:)
<azonenberg_work>
"From a synthesis tool perspective, a "full" case statement is a case statement in which everypossible binary pattern is included as a case item in the case statement."
<azonenberg_work>
i'm going to test more thoroughly but i think this is a bug
<azonenberg_work>
And there are few uses for them :)
<azonenberg_work>
i've never needed either
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<azonenberg_work>
rqou: ok sooo
<azonenberg_work>
it's less dumb than i thought
<rqou>
async set/reset inference is still dumb :P
<azonenberg_work>
"proc" will infer a latch, then optimize it out because the clock pin is always high
<azonenberg_work>
if you have all cases covered
<azonenberg_work>
So i guess its not a bug, just a bit inefficient
<azonenberg_work>
async set/reset is indeed udmb
<azonenberg_work>
buuuut i have a higher priority thing to work on now
<azonenberg_work>
:p
<rqou>
you should fix latch set/reset/gate priorities if you can
<rqou>
because we actually need that
<azonenberg_work>
In case i didn't have enough stuff on my plate... :p
<azonenberg_work>
short term, i need to be able to present my con talk
<azonenberg_work>
everything else is secondary
<azonenberg_work>
i have other stuff to do tonight but tomorrow after work i'm going to try and bang out some cool figures showing the decompilation steps
<enriq>
I have my design in vhdl so I should start writting jed soon :)
<enriq>
as soon as this nasty work finishes
<enriq>
damm money
<enriq>
I was wondering, just without thinking too much... how would a state machine map to the coolrunner
<azonenberg_work>
Pretty well, i would think - that's what they are designed for
<azonenberg_work>
But you really should just write it in verilog and poke rqou to finish his place-and-route
<azonenberg_work>
(or, better yet, help)
<rqou>
lol
<rqou>
it's getting closer
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<enriq>
I think I need to do a place and route by hand first to understand, no?
<enriq>
but ok I will translate to verilog if I can
<azonenberg_work>
Depends
<enriq>
I could not really understand verilog very well
<azonenberg_work>
Is your goal to understand how CPLDs work?
<azonenberg_work>
at a very intimate level?
<azonenberg_work>
Or to get your project done
<enriq>
I mean to help rqou
<enriq>
no, I want my project done
<enriq>
but you want my hand written jed
<azonenberg_work>
It would be helpful but i can live without it
<azonenberg_work>
i can make some simple test thing
<azonenberg_work>
Basically, the only reason to hand write a jed (vs using rqou's tool) is if you need something simple done right now, before he finishes
<azonenberg_work>
or if you want to learn the chip inside out and help him write it
<rqou>
or if you want to use XORs? :P
<azonenberg_work>
Or if you're just curious
<azonenberg_work>
Lol :p
* rqou
still needs to poke alanmi
<enriq>
ok so my homework is translate to verilog and make it work with icarus as I have it working with ghdl
<rqou>
you should test if yosys can synthesize it to its own internal cell library
<enriq>
or else what
<rqou>
(yosys and icarus don't always do exactly the same thing)
<enriq>
ok so I rewrite in verilog and run it thru yosys
<enriq>
I barely understand what yosys does
<enriq>
I guess I'll have to study
<enriq>
this is where my hobby starts looking like a job
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