<pointfree>
So it says AIG's are a subset of MIG's.
<rqou>
sure
<rqou>
the paper i found was using MIGs to extract carry chains
<rqou>
which was supposed to be better than the hack that i'm using
<rqou>
*better for actual synthesis, not for RE
<pointfree>
I like how they can choose to optimize for depth-size-activity, or delay-area-power, etc. Trying to figure out why this might be better than AIG's.
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<pointfree>
(Like azonenberg and you rqou I'm also looking to use logic synthesis for RE)
<pointfree>
I don't have a SEM so I send input patterns to chips. I've focused on resolving camouflaged gates for now.
<pointfree>
Previously I was using incremental logic synthesis with BDD's + quantifiers but now I'm looking to make the jump to AIG's or MIG's.
<balrog>
pointfree: is this PSoC related or something else?
<pointfree>
balrog: It is related although I would't run an SAT solver on a PSoC.
<pointfree>
wouldn't*
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<eduardo__>
felix_: yes, please semd me the voucher. I did add myself to the Metalab list. clifford already got a speaker voucher. WE will do a FPGAassembly again. Did debug HW yesterday at Daniels Lab where you manufacture the Apertus camera.
<eduardo__>
Yes. Cotton seed lose interest. But clifford can pull too into ArachnePnR. So tell him.
<eduardo__>
I once had an email exchange with the professor at columbia who did the FPGA project. seems to be a cool guy.
<eduardo__>
azonenberg: Clifford and I do start an open Source EDA company in September and will work with our first large client on the tools (mainly formal verification). We will hire two additional programmers in 1Q2018. We do have funding for 24 months and hope to ramp up revenue so that we can be self sustained in 2020. We are able to get additonal funding for making chips once it makes sense . We hope that business will be good, so t
<eduardo__>
hat we will be able to hire more hackers working on opensource EDA tools. Its all a big experiment and we really try to run on a shoestring budget.
<eduardo__>
pointfree: do you have a webpage about your PSOC work where I can point someone to?
<eduardo__>
I got someone who was fascinated by your work when I told him as he did some projects with the PSOC. And he is into reversing FPGAs :-)
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<cyrozap>
^ is relevant to the topic because they actually decapped and delayered the CPU to extract microcode ROM
<pointfree>
eduardo__: Great to hear!
<pointfree>
I should indeed assemble some kind of webpage for the PSoC stuff to replace the open directory. There's the openfpga/yosys stuff as well as the gelForth project for interactively compiling high level code to digital logic from a repl. Forth is the first target, but I'm hoping it will be simple and easily portable to other languages as well.
<pointfree>
I'm moving things over to github and I can put together a web page tomorrow morning if that works (I'm in California).
<pointfree>
The open source EDA company sounds awesome btw.
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<rqou>
um, why did a whole bunch of people get k-lined?
<pointfree>
rqou: This might have to do with handling the massive wave of spam PM's on freenode this evening. Don't click the links!
<rqou>
hmm, i haven't gotten any
<pointfree>
rqou: I got a lot of them until I blocked unregistered nicks from sending PMs to my nick (which I thought I had already done during the previous spam wave).
<rqou>
although for the longest time i wasn't registered either
<pointfree>
rqou: The k-line'ing was aparently a mistake on the part of the freenode staff.
<rqou>
i finally registered after i set up fpgacraft1 and fpgacraft2 because their C&C is whitelisted by nick
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<pointfree>
I do get a lot of useful PM's from unregistered nicks... but I don't ever want to get cp spam messages ever again.
<rqou>
oh ugh
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<DocScrutinizer05>
yeah /umode +R
<DocScrutinizer05>
I got klined too. Seems they reverted that oopsie :-)
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<JSharp>
yeah, it's been wild due to the PM spam
<JSharp>
ugly griefing... nasty stuff
<JSharp>
glad I disabled image embedding in my client :/
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<felix_>
rqou: please give the next voucher to eduardo
<eduardo>
thanx
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<eduardo>
rqou: for how long will you stay in Europe/Germany during 34C3 ?
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<jn__>
cyrozap: interesting paper! (the one about K8/K10 microcode)
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<pie_>
azonenberg, how do you know what standard cell a given circuit on silicon is?
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<pie_>
" This site contains support material for a book that Graham Petley is writing, The Art of Standard Cell Library Design. " http://www.vlsitechnology.org/
<pie_>
> no book
<pie_>
> not updated in 4 years
<pie_>
> :C
<qu1j0t3>
pie_: Ken Shirriff has a video that touches on that
<qu1j0t3>
pie_: There's other textbooks that might help, I have one titled "Application SPecific Integrated Circuits", Michael John Sebastian Smith
<pie_>
noted.
<pie_>
\o/
<qu1j0t3>
Mead & Conway is also free online i think
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