egg|work|egg has joined ##openfpga
mtp has joined ##openfpga
JSharp is now known as Guest50158
balrog has joined ##openfpga
Zorix has joined ##openfpga
kmehall has joined ##openfpga
pointfree1 has joined ##openfpga
scrts has quit [Ping timeout: 240 seconds]
<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v757Y
<openfpga-github> yosys/master 3c39135 Andrew Zonenberg: Updated PGEN model to have level triggered reset (matches actual hardware behavior
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/v7572
<openfpga-github> openfpga/master 6f4420d Andrew Zonenberg: Added UART test
azonenberg_work has joined ##openfpga
azonenberg_work has quit [Client Quit]
scrts has joined ##openfpga
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/v755t
<openfpga-github> openfpga/master de40bdd Andrew Zonenberg: gpkjson now aborts correctly when loading the input fails
Guest87734 has joined ##openfpga
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/v755x
<openfpga-github> openfpga/master bfe44cb Andrew Zonenberg: Fixed glitch in UART test
balrog has quit [Quit: Bye]
balrog has joined ##openfpga
azonenberg_work has joined ##openfpga
digshadow has quit [Ping timeout: 240 seconds]
mewyn has quit [Ping timeout: 255 seconds]
mewyn has joined ##openfpga
DingoSaar has quit [Remote host closed the connection]
cr1901_modern has quit [Ping timeout: 240 seconds]
scrts has quit [Ping timeout: 240 seconds]
ZipCPU|Laptop has quit [Ping timeout: 240 seconds]
scrts has joined ##openfpga
<azonenberg> Sooo i managed to make a simple uart test case in a greenpak
<azonenberg> Smaller than i thought it would be
<azonenberg> Four luts, two dffs, two inverters, two counters, and the lut/pgen
<azonenberg> for something that sends "A" in a loop about 30 Hz
<rqou> good for you :P
<rqou> i'm currently entering data into my calendar and reading syllabi :P :P
<azonenberg> Lol
<rqou> totally ready for class :P
<azonenberg> Well the fun bit is, now that i have this uart
<azonenberg> i want to RE it :)
<rqou> somehow UCB gimped their course scheduler and it no longer as ical export
* azonenberg notes GP_PGEN loading is not implemented in gpkjson yet
<rqou> also for whatever reason android's calendar app _sucks_
<azonenberg> I think REing this with my flow will be the goal
<rqou> which is ironic because that was one of the original selling points of PDAs
<azonenberg> whats wrong with it?
<azonenberg> my only complaint is that i cannot create events that start and end in different time zones
<rqou> i just find it super annoying to create events correctly, especially repeating ones
<rqou> it keeps trying to be too clever
<azonenberg> only way i've found to do that is to enter it in the google apps web calendar then sync to phone
<rqou> right now i'm giving up and entering the information on the web app
digshadow has joined ##openfpga
<Ellied> someone should make a port (or at least a convincing copy) of the original Palm calendar app to Android
Guest50158 has quit []
Guest50158 has joined ##openfpga
Guest50158 is now known as JSharp
JSharp has quit [Client Quit]
JSharp has joined ##openfpga
mewyn has quit [Quit: WeeChat 1.4]
_whitelogger has joined ##openfpga
scrts has quit [Ping timeout: 260 seconds]
scrts has joined ##openfpga
azonenberg_work has quit [Ping timeout: 246 seconds]
mtp has quit [Quit: Who ever quits IRC?]
digshadow has quit [Ping timeout: 240 seconds]
mtp has joined ##openfpga
scrts has quit [Ping timeout: 240 seconds]
scrts has joined ##openfpga
teepee has quit [Ping timeout: 248 seconds]
teepee has joined ##openfpga
teepee has quit [Ping timeout: 255 seconds]
teepee has joined ##openfpga
specing has joined ##openfpga
<eduardo__> rqou: if you do have you 34c3 ticket, you can forward your voucher to someone else (like me :-) I would love to organize an openSource FPGA assembly again. I will travel with clifford again.
<rqou> i don't yet because my bank is being stupid
<eduardo__> felix: I would like to have a ticket. But I might get one through Metalab (hackerspace in vienna). So if you only have one, then spare it to someone who really needs it.
<rqou> apparently my bank doesn't seem to be super happy with me paying $Infinity in tuition and charging a foreign transaction all at the same time
lexano has quit [Ping timeout: 240 seconds]
lexano has joined ##openfpga
teepee has quit [Ping timeout: 245 seconds]
azonenberg_work has joined ##openfpga
teepee has joined ##openfpga
scrts has quit [Ping timeout: 246 seconds]
<eduardo__> rqou: should I do the 34c3 payment for you and you later give me the money?
<rqou> no it's stuck in a mystery state right now
<rqou> i'm going to give it another day to try clearing
scrts has joined ##openfpga
<rqou> gotta love US banking
<rqou> whenever something breaks it will just silently fail until the banks manage to FTP around enough state to tell you what happened
lexano has quit [Ping timeout: 240 seconds]
lexano has joined ##openfpga
<azonenberg> rqou: gotta love paying off your credit card and then having your account summary show either a few $K disappearing or duplicated for a day or two
<azonenberg> is the rest of the world that screwed up?
* azonenberg knows zilch about how SWIFT etc work
<gruetzkopf> SWIFT Land transactions are much more sane
<rqou> i heard SEPA is great?
<gruetzkopf> And people tend to use debit cards, not credit cards
<azonenberg> idk, i like credit cards
<azonenberg> The money sits in my account earning interest for another month before i pay the bill
<azonenberg> As long as i pay it on time, there's no interest or fees
<rqou> the US also loves "cash back" credit cards that according to various studies help keep rich people rich :P
<azonenberg> And the companies give me all kinds of perks in hopes of convincing me to spend more money than I have
<gruetzkopf> People were grumbling because change ( most 'New' sepa features were already available in germany
<gruetzkopf> but it's fairly useful
<azonenberg> rqou: hey, as long as you only spend money you can afford to spend i'm fine with it
<gruetzkopf> i pay 0 per SEPA transaction
<azonenberg> You just have to not spend more than you can comfortably pay off
<azonenberg> from my perspective it's a 1.5% discount on all purchases, plus an extra month of that money earning interest in my checking account before i give it (indirectly) to the vendor
<azonenberg> The CC companies hate people like mey
<azonenberg> me*
<azonenberg> they also hate the high risk folks who default and make them lose money
<rqou> and then this gets folded into CC processing fees and makes merchants sad
<azonenberg> The ones they love are the ones that pay their bill eventually, but after a while
<gruetzkopf> checking accounts don't usually get any interest here
<azonenberg> With interest and late fes
<rqou> oh yeah, the US has interest-bearing checking, which is also weird
<azonenberg> Because that's where the bank gets rich
<azonenberg> rqou: Because american banks don't just hold onto your money and keep it safe
<azonenberg> they loan it out to everyone else
<rqou> but all banks do that
<gruetzkopf> also mailing around paper has been dead for decades here
<azonenberg> Pretty sure ours are bigger offenders
<azonenberg> gruetzkopf: It's dying here, slowly
<azonenberg> I do not own a physical checkbook
<gruetzkopf> basically since the 60s
<rqou> i still occasionally have to use physical checkbooks
<azonenberg> my bank mails paper checks on request from their central office, which i do once every two months to pay for my garbage service (that company apparently doesn't do electronic payments)
<rqou> which is super dumb, because it eventually turns into a row in a fixed-width text file that is FTP'd to the federal reserve
<gruetzkopf> getting 2 checks a day cashed in at a bank was unusual in the 90s according to my mother
<rqou> and if you do what azonenberg does, then you have a number in a computer that turns into dead tree that is immediately turned back into a number in a computer
<rqou> (which then goes into a text file, into FTP, etc.)
<azonenberg> Indeed, lol
<azonenberg> Can we just nuke the FTP and dead trees
<azonenberg> and just have point to point sockets?
<rqou> i don't think the mainframes at the fed support sockets
<azonenberg> is it really that hard for all tier-1 banks to have TLS streams to each other
<rqou> :P
<rqou> can your mainframe do TLS? :P :P
<azonenberg> It doesnt have to go to the mainframe
<azonenberg> It can terminate at a bridge box that then FTPs over the LAN, if you have to
<rqou> you'd need to port openssl to cobol first :P
<gruetzkopf> here they've been doing online transactions forever
<rqou> gotta put on the IBM-branded necktie before you start :P :P
<azonenberg> But it would allow realtime vs bridged transaction processing, and provide an upgrade path
<gruetzkopf> through the federal x25 network
<azonenberg> for when mainframes finally die like they should have in the 1980s
<azonenberg> :p
<rqou> but azonenberg, your proposal adds a new machine, and it's not IBM-branded
<azonenberg> Correct, it's a pile of bog-standard linux boxen
<azonenberg> running a distributed file system
<azonenberg> with sockets between them to replicate content
<azonenberg> and ensure synchronization
<gruetzkopf> current s390x mainframes (z13, z14) support TLS quite well
<rqou> but that's not enterprisy and can't be programmed in cobol
<gruetzkopf> :P
<azonenberg> When I hear "enterprise" it makes me want to vomit
<azonenberg> so, fine by me :p
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/v7dtn
<openfpga-github> openfpga/master e2c9aae Andrew Zonenberg: Implemented load support for Greenpak4PatternGenerator
<rqou> wow you're leaving for vacation tomorrow and you're still coding?
<azonenberg> I'm not
<azonenberg> Their flight lands at in a bit over 12 hours
<azonenberg> Then they have to get the rental car, drive here
<azonenberg> Then we go shopping for noms plus stuff like fuel that they couldn't fly in with
<azonenberg> Then we spend the night here and leave weds morning
<rqou> ah
<azonenberg> And it's not like i have much to pack, I'm always ready to run out into the woods for 48 hours on a few minutes' notice
<azonenberg> basically however long it takes me to fill up my water bottles
<azonenberg> and google directions to the base location
<rqou> i had you marked as not available tomorrow but i guess that was just because you had to go and do "stuff"
<rqou> not because you were leaving
<rqou> it's great because i won't be available for two weeks either :P
<azonenberg> So going on a camping trip is basically, grab the pack that's already staged and throw it in the car
<rqou> (yes, including the weekend)
<rqou> (yes, there is class on saturday)
<azonenberg> then add a bit of extra food and clothing for a prolonged trip
teepee has quit [Ping timeout: 240 seconds]
<rqou> fortunately there is only class on the weekends this week
<rqou> unfortunately this blocks out "request cleanroom access" for the month
<azonenberg> oh well
teepee has joined ##openfpga
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/v7dtV
<openfpga-github> openfpga/master ff11bd3 Andrew Zonenberg: Fixed bug in PGEN bitstream loading
<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v7dty
<openfpga-github> yosys/master e0e68f0 Andrew Zonenberg: Fixed more issues with GreenPAK counter sim models
teepee has quit [Ping timeout: 258 seconds]
teepee has joined ##openfpga
test123456 has joined ##openfpga
_whitelogger has joined ##openfpga
scrts has quit [Ping timeout: 240 seconds]
scrts has joined ##openfpga
cr1901_modern has joined ##openfpga
Hootch has joined ##openfpga
scrts has quit [Ping timeout: 240 seconds]
<felix_> eduardo__: i got one voucher for the openfpga project that replicates until all tickets from this part of the presale a sold out. having you organize the assembly sounds good :) only balrog said that he might be interested in getting a ticket, but i'd still say that it would be a good idea that you also add yourself to the ticket buying queue from the metalab; if you get the ticket via our voucher
<felix_> faster, then just pass the metalab one to the next person in the queue
* felix_ will probably busy with the videoactive project (open source sdi implementation for apertus axiom beta and timvideos' hdmi2usb). i hope that we have an axiom beta with sdi output for the congress that can be hooked up to the c3voc recording system and used maybe as second camera for recording of the talks
coino has joined ##openfpga
ZipCPU|Laptop has quit [Quit: Transitioning to a lower energy state]
scrts has joined ##openfpga
teepee has quit [Ping timeout: 248 seconds]
teepee has joined ##openfpga
Jarth has joined ##openfpga
teepee has quit [Ping timeout: 255 seconds]
teepee has joined ##openfpga
ZipCPU has quit [Ping timeout: 255 seconds]
Jarth has quit [Quit: Leaving]
Jarth has joined ##openfpga
ZipCPU has joined ##openfpga
Jarth has quit [Ping timeout: 240 seconds]
<balrog> I noticed that there are several open PRs to arachne-pnr that haven't been looked at in a while
<balrog> did Cotton Seed lose interest? :/
teepee has quit [Ping timeout: 245 seconds]
teepee has joined ##openfpga
<openfpga-github> [yosys] azonenberg pushed 4 new commits to master: https://git.io/v7Fe9
<openfpga-github> yosys/master e991836 Clifford Wolf: Merge branch 'azonenberg-rmports'
<openfpga-github> yosys/master 88983f5 Clifford Wolf: Mostly coding style related fixes in rmports pass
<openfpga-github> yosys/master 9fe6bc4 Clifford Wolf: Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg-rmports
wpwrak has quit [Read error: Connection reset by peer]
wpwrak has joined ##openfpga
<openfpga-github> [yosys] azonenberg deleted rmports at 15e41d6: https://git.io/v7FTh
<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v7Fkl
<openfpga-github> yosys/master 6a6ecb0 Andrew Zonenberg: Removed rmports since it was renamed
<openfpga-github> [yosys] azonenberg created gpak-counters (+4 new commits): https://git.io/v7FkX
<openfpga-github> yosys/gpak-counters e510984 Andrew Zonenberg: Fixed bug in GP_COUNTx model
<openfpga-github> yosys/gpak-counters 3a404be Andrew Zonenberg: Updated PGEN model to have level triggered reset (matches actual hardware behavior
<openfpga-github> yosys/gpak-counters 66b256d Andrew Zonenberg: Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high
<openfpga-github> [yosys] azonenberg created recover-reduce (+3 new commits): https://git.io/v7FIn
<openfpga-github> yosys/recover-reduce b858450 Robert Ou: recover_reduce: Add driver script for the $reduce_* recover feature...
<openfpga-github> yosys/recover-reduce 858c5ca Robert Ou: recover_reduce_core: Finish implementing the core function
<openfpga-github> yosys/recover-reduce b30ce44 Robert Ou: recover_reduce_core: Initial commit...
<azonenberg> woo merging
<azonenberg> Still have to get the recover_* passes merged, plus a few more fixes to sim models, but we're getting closer
<azonenberg> lol
<qu1j0t3> pie_: It works for everything!
pie_ has quit [Ping timeout: 260 seconds]
<balrog> cseed> After writing arachne-pnr I took a new job and haven't much time to continue working on it.
<balrog> well, that's too bad
Hootch has quit [Read error: Connection reset by peer]
specing has quit [Ping timeout: 248 seconds]
digshadow has joined ##openfpga
specing has joined ##openfpga
Hootch has joined ##openfpga
coino has quit [Ping timeout: 260 seconds]
egg|work|egg has quit [Ping timeout: 260 seconds]
eduardo_ has joined ##openfpga
eduardo__ has quit [Ping timeout: 246 seconds]
Hootch has quit [*.net *.split]
scrts has quit [*.net *.split]
azonenberg_work has quit [*.net *.split]
mtp has quit [*.net *.split]
scrts_ has joined ##openfpga
Hootch has joined ##openfpga
mtp has joined ##openfpga
mtp has joined ##openfpga
mtp has quit [Changing host]
azonenberg_work has joined ##openfpga
Hootch has quit [Quit: Leaving]
pie_ has joined ##openfpga
test123456 has quit [Quit: Leaving]
<azonenberg> balrog: do you have access to the wiki?
<balrog> azonenberg: yeah
<azonenberg> Make a page with prior art on open FPGA hardware
<azonenberg> and throw in anything you find
<balrog> on the EDA wiki?
<azonenberg> no on the github
<balrog> ahhh ok
<balrog> don't think I have access there, hm
<azonenberg> Whats your github username?
<balrog> hang on a bit
<azonenberg> rqou: so i just checked github stats after clifford merged a bunch of our PRs
<azonenberg> the contribution log is showing the usual exponential decay
<azonenberg> clifford is waaaaaay up there with the vast majority of the code (it's still largely a one-man project), then i'm a distant second, you're #4, then several dozen people with 1-2 small commits each
<azonenberg> conclusion, we need more EDA nerds to get involved :p
<balrog> azonenberg: how do we decrease the barrier of entry? :)
<balrog> (meaning, making this stuff in general more accessible to people new to it, but who have a lot of software background)
<azonenberg> That's a good question and I'm not sure i have a good answer
<azonenberg> Writing EDA tools requires that you be fairly experienced with both software development and digital logic
teepee has quit [Ping timeout: 240 seconds]
<azonenberg> if you don't know s/w you end up writing awful unmaintainable EE code (we've all seen this)
<azonenberg> if you don't know H/W, your code ends up being of little practical use because it doesn't do what engineers actually need
<balrog> yeah :(
<azonenberg> In general, people who know both well are rare
<azonenberg> i mean people who are familiar with version control and maintaining large software projects, debugging, etc
<azonenberg> actual software engineering rather than just knowing the language
<balrog> yes
<azonenberg> while also knowing digital logic etc
<cr1901_modern> azonenberg: Well someone did say, "if there were 5 ppl putting the work in that clifford does, the EDA ecosystem would look vastly different"
teepee has joined ##openfpga
<cr1901_modern> My main barrier to contributing meaningfully, is quite frankly, $$. But if I had $$, I also wouldn't have time. If I had $$ and time, I wouldn't have energy. Pick two.
<balrog> $$ to acquire development hardware, or what?
<cr1901_modern> ^ This. And money to spend on acquring the skillset of making PCBs on the level azonenberg can
<balrog> development hardware for smaller chips is not that expensive
<balrog> and PCB design... yeah
<balrog> but that's not needed for a lot of things
<azonenberg> cr1901_modern: do you have a cheap/slow LA and oscilloscope?
<azonenberg> low tens of MHz is enough for greenpak work
<cr1901_modern> former yes (can make icestorm SUMP work), latter no.
<balrog> low tens of mhz... is a saleae-clone good enough?
<cr1901_modern> azonenberg: More specifically, I have FPGA boards up to the task of a cheap logic analyzer, and I have some Agilent probes that were a gift some years back
<azonenberg> balrog: the highest freq oscillator in greenpak is the 27 MHz ring oscillator, next highest is the 2 MHz R-C
<azonenberg> and the ring osc is normally pre-divided before use
<cr1901_modern> I wonder if you could hand solder the GP package... I learned how to SMD solder last year, and was able to solder an inductor with pads exclusively on the bottom
<azonenberg> Anyway, if you have that, you can probably help a lot with the greenpak toolchain
<azonenberg> cr1901_modern: you probably could, but a toaster oven is $20 at walmart
<azonenberg> and a tiny oshpark breakout PCB is maybe $5
<azonenberg> why bother?
<balrog> cr1901_modern: do you have a hot air station?
<azonenberg> also the devkit comes with zif sockets
<cr1901_modern> whitequark gave me a few breakout PCBs last year
<cr1901_modern> balrog: No :(
<balrog> then you need a toaster oven
<cr1901_modern> azonenberg: What toaster oven did you used to use?
<cr1901_modern> I know you got a new one, but you had a cheap old one that could do BGA 1.0mm
<cr1901_modern> IIRC*
<azonenberg> I did smaller stuff in that oven, it just lacked uniformity b/c it had no fan for forced convection
<azonenberg> fine pitch was no big deal, large boards were problematic
<azonenberg> regardless of pitch
<cr1901_modern> define large?
<azonenberg> more than maybe 2-3" in the short axis
<azonenberg> The long axis could go down the heating element axis and anything that fit in the oven was fine
<rqou> wait how am i yosys contributor #4? that sounds wrong
<azonenberg> rqou: lol
<azonenberg> clifford has ~2800 commits, i have 150ish, somebody else has like 30ish, you're next in line
<cr1901_modern> Well, what model oven do you use now? I'll buy an oven, but I want to buy something that I know has worked for other people.
<azonenberg> idk if it ranks by LoC or commits, the graph shows both
<cr1901_modern> So I can remove all failure sources except, well, me
<azonenberg> cr1901_modern: let me try and find a pic of it...
<azonenberg> really it doesnt matter :p
<azonenberg> anything that heats to at least 450F and has a convection fan is fine
<cr1901_modern> what's the name of that solder paste that doesn't need refrigeration?
<azonenberg> no idea
<rqou> azonenberg tells me he just doesn't refrigerate his
<azonenberg> i use whatever kester stuff oshstencils sells
<azonenberg> and just chuck it when it starts to act funny
<balrog> loctite gc10
<balrog> lasts a year without refrigeration
<balrog> probably longer
<balrog> rated for a year at 26.5 C / 80 F
<azonenberg> cr1901_modern: I think this is my oven https://www.walmart.com/ip/Farberware-25L-Digital-Toaster-Oven/46707182
<azonenberg> i put the PCB on standoffs on top of the black drip pan it comes with, put it on the middle rack
<azonenberg> select the "cookies" setting (both heating elements on, fan on)
<cr1901_modern> standoffs?
<azonenberg> dial temp to max
<azonenberg> (450F)
<azonenberg> cook with no profiling until i see the solder melt across the whole board
<azonenberg> wait 15 sec, turn off heat, wait 15 sec, open door
<balrog> people complain that this paste is sticky and will stick to walls of thick stencils, though
<cr1901_modern> I don't think I have standoffs
<azonenberg> cr1901_modern: any little heat-resistant object will work as long as you can get 4 of the same thickness
<azonenberg> scrap pcbs, even
<cr1901_modern> (also lol @ cookies setting. Bake until your PCB is warm and chewy)
<azonenberg> basically you want to lift the board up a bit so that it doesn't touch the pan
<azonenberg> the pan itself acts as an IR barrier to prevent radiant heat from overheating the pcb underside (you want the top warmer)
<azonenberg> then the standoffs ensure the board is primarily heated by convection, and radiation on the top
<cr1901_modern> Well 4 scrap PCBs of the same thickness I def have
<azonenberg> rather than conduction from the pan
<azonenberg> which would result in uneven heating
<balrog> that's where some of the tools efabless has are located
<azonenberg> Also you dont want the underside of the pcb touching anything during reflow if it has components on it
<balrog> with source and al.
<balrog> all*
<azonenberg> because if the solder melts and the pcb is touching anything it might shift position and push them off
<azonenberg> you want them just dangling held in place by surface tension
<qu1j0t3> azonenberg | cr1901_modern: any little heat-resistant object will work as long as you can get 4 of the same thickness || I use balls of rolled up foil. Works nicely
<qu1j0t3> you can shape em so they clasp the corners of the board, etc.
<cr1901_modern> Cool, so the toaster oven needs:
<cr1901_modern> 3. Heating elements on top and bottom
<cr1901_modern> 2. 450 F
<cr1901_modern> 1. A fan
<cr1901_modern> And my scrap PCBs... they're all 2 layer from oshpark. That thick enough?
knielsen has joined ##openfpga
knielsen has quit [Ping timeout: 248 seconds]
<cr1901_modern> azonenberg: I'm sorry dangling?
<cr1901_modern> qu1j0t3: Do you have a picture? I'm having trouble visualizing this
<azonenberg> Back
<azonenberg> Yeah it doesnt matter what they are as long as they're the same thickness and heat resistant
<azonenberg> i use little metal clips from something
<azonenberg> i've also used metal pcb standoffs
<azonenberg> or scrap pcbs
<azonenberg> As far as height above the surface, what matters is that there's no direct contact with the highest component on your underside
<azonenberg> so almost anything will work for a board with top side components only
<azonenberg> if you have a big 1210 sized cap on the underside, you'll want probably 2+ mm of clearance
<azonenberg> maybe 3-4
<qu1j0t3> cr1901_modern: no, but just imagine a 1/2" ball of aluminium cooking foil
<qu1j0t3> cr1901_modern: you can jam the sharp board corners into it, e.g., or just rest on
<qu1j0t3> cr1901_modern: anyway it works if there's nothign else
<cr1901_modern> qu1j0t3: Ahhh, well if I use your advice, I'll just take a pic/ask you before I turn the oven on :3
<rqou> damn, apparently UCB got smarter and takes my old ID when i request a new one
<balrog> rqou: physical ID cards?
<balrog> so if you "lose" your card, you have to pay a fee?
<azonenberg> rqou: at rpi you could report it as lost/damaged and not hand it over
<azonenberg> they'd charge you extra
<rqou> i probably should have lied and said i don't have my old card anymore
<rqou> oh well
<balrog> is there currently a way to "disassemble" a PSoC5LP bitstream?
<balrog> cyrozap, pointfree ^
<balrog> not into RTL/netlist but into lower level data
<pointfree> balrog: I have a tool that disassembles config.hex (the bitstream format) into lists of: <value> <register> <regname>
<balrog> pointfree: yeah that's what I meant
<rqou> hey, illegal question: anybody have Clipper DESfire keys?
<rqou> i now have an "unlimited bus rides" Clipper card and I'm curious how that is encoded
<pointfree> balrog: I'm putting it into a fresh new repo with a little documentation for ya.
<balrog> pointfree: where?
<balrog> also you were working on a tool to work with DSI, right?
<balrog> I have all these PSoC boards so I should do something, and the TRMs are more detailed than I remember :)
<pointfree> balrog: I'm just cleaning it up real quick before I upload it.
<pointfree> I think I've figured out the DSI port interface mappings. Will upload what I have there too.
<balrog> also huh, spartan-7 now in production?
<pointfree> It would be great to get some help with live hardware tests of the register mappings from someone, if that's what you were thinking of doing :)
<balrog> I was going to poke at the analog stuff, but that seems well documented
<balrog> if you want live hardware tests I can easily do that, though I need to know what test equipment I should be using
<balrog> since my test equipment is spread across different places in the city :P
<azonenberg> :p
<azonenberg> pointfree: Sooo
<pointfree> balrog: You would just need a CY8CKIT-059. The blue led (P2.1) can be used for feedback until it's time to test the other peripherals connected to the DSI.
<pointfree> balrog: The Cypress engineers at Maker Faire said the analog array would be more challenging to RE, so I think there will be plenty to do there :)
<azonenberg> if i wanted to get a dump of a psoc5lp bitstream
<azonenberg> in yosys json format
<balrog> azonenberg: have you looked at the TRMs?
<azonenberg> along with a set of verilog models of any digital hard IP you're using
<azonenberg> how long would that take you?
<azonenberg> balrog: skimmed it, but i'm asking more about implementation
<azonenberg> afaik the RE is done already
<balrog> it's more that the chip is full of hard IP
<azonenberg> well yeah :p
<balrog> and has countless registers to control it
<azonenberg> i'm talking about just the digital fabric for now
<azonenberg> to start
<azonenberg> we can work out from there
<balrog> ahh, the UDBs and routing fabric for those?
<azonenberg> Yeah
<azonenberg> and maybe datapath blocks within the udbs
<balrog> pointfree: was is you who had an online tool to explore routing?
<balrog> pointfree: well I have a cY8CKIT-059 right here in front of me
<balrog> pointfree: they give you a nice map of the analog routing on page 321 of the architecture TRM
<balrog> that said it's still a mess
<pointfree> balrog: Not sure which tool you are talking about in particular, but I have a trick where I can use just two 32 bit bitmasks as a quantified boolean formula. WIth just two bitmasks I can do things like list all Vertical Segment 7's or all OR terms in bank 1 etc, etc.
<pointfree> balrog: The psoc logic fabric is almost beautifully (and also tanalizingly) regular. I've been almost there for too long. It would be great to put more heads together on this. The reason I care about this regularity and don't just leave it with a lookup table is because of on-chip live reconfiguration (from the UDB status & control blocks).
<pointfree> Should I stop being a loner and put this stuff on github instead of a darcs repos?
<balrog> please use git
<balrog> dunno why you like darcs so much :<
<azonenberg> yes that would be nice
<balrog> (darcs lost the DVCS war long ago, as did monotone... mercurial held out the longest)
<balrog> not saying it's all bad but... good luck getting anyone to use it :P
<pointfree> oh alright. I'll use git for openfpga stuff until https://pijul.org/ matures more. I think pijul has a future, but yeah, darcs is probably a lost cause :(
<mtp> i'm the one Fossil wank
<azonenberg> pointfree: we have the github repo in the topic for a reason
<balrog> (obligatory xckd)
<balrog> xkcd*
<pointfree> :_(
<balrog> and yeah, I dislike a lot of things about git :(
<balrog> but I can generally bend it to my will
<pie_> i should try darcs one of these days
<pie_> balrog, should just make all the other dvcs frontend as bad / the same as git and then it wont matter which they use :D
<balrog> pointfree: well let me know when there's something to test :)
<pointfree> balrog: yup.
<mtp> you know the --interactive/--patch modes to git? darcs did that by default and was better about it
coino has joined ##openfpga
<pointfree> crypto software is one thing I won't put in a git repo.
<balrog> Heh, why not?
<pie_> cuz its not sekur against enlightened tamperinh?
<pie_> hm actually an exploit in git would be pretty amusing
<balrog> mtp: mercurial did a lot of good stuff and still lost (Python eventually moved to Git)
<balrog> pie_: you're talking about exploit or collision?
<pie_> the former
<pie_> im not sure how to feel about the latter but it bothers me that git is hardcoded to sha256
<mtp> balrog, i had to use bzr once and it was the worst
<pie_> though apparently theres been *some* work to make git primitive independent
<rqou> i tried to use bzr to clone the kicad repo before they moved to git and it was slow as shit
<mtp> `bzr pull` is O(n) in terms of number of commits in the repo in order to tell you that there was nothing to pull
<balrog> how about monotone?
<pointfree> balrog: because what appears to be a clean merge may not have been a correct merge. What you review is not necessarily what you get. Git's fuzzy merging becomes dangerous when you are versioning crypto software. I would rather use no automatic merging at all than use git ...but anyway, git is as close as you can get to using no vcs at all.
<mtp> all i know about it is that it's the Ada of version control systems
<mtp> according to their site
<mtp> and that's not exactly a glowing recommendation
<balrog> pointfree: well, I review all merges manually
<balrog> mtp: it was customary to provide the repo as a download since initial clone through monotone is very slow and network heavy
<balrog> Pidgin used it
<balrog> They eventually switched to Mercurial
<pie_> im not sure about the quality of pidgin, to be fair i havent seen the source, not that id be able to tell
<mtp> yeah "pidgin used it" is an antirecommendation
<mtp> pidgin's protocol plugins are the swissest of cheeses
<pie_> haha
enriq has joined ##openfpga