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<rqou> also, neo geo cartridges are nuts :P
<rqou> they have something like 5 different parallel busses
<rqou> azonenberg_work: do you know how long a s6 takes to boot?
<rqou> alternately, how long does a gp4 take to boot? worst case i can use a gp4 to supply vectors and an infinite loop until the real fpga boots up :P
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<azonenberg_work> rqou: re s6 boot time
<azonenberg_work> what density
<azonenberg_work> and what boot media?
<azonenberg_work> you have a fixed latency of maybe 30 ms (datasheet says it can be as fast as 5) for power-on reset
<azonenberg_work> Then the boot time depends on the bitstream size, bus width, and clock rate
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<azonenberg_work> Fast: xc6slx9 (2.7 Mbits), max SPI clock rate (50 MHz), x4 bus width gives 2.7 Mb / 200 Mbps = 13.5 ms
<rqou> that's still pretty slow
<rqou> what's the boot time of a gp4/coolrunner-ii like?
<azonenberg_work> Slow: xc6slx150t (34 Mbits), slow SPI clock rate (2 MHz), x1 bus width gives 34 Mb / 2 Mbps = 17 sec
<azonenberg_work> :p
<azonenberg_work> artix can boot faster, i think
<rqou> but i need a part that boots before the host console boots
<rqou> which never seems to have been clearly documented how long that takes
<azonenberg_work> 7 series... 10 to 35 ms POR time, then say an xc7a25t is 99 Mb
<azonenberg_work> 9.9*
<azonenberg_work> So probably slower, but i think the fmax is higher
<azonenberg_work> The config time for an xc2c32a is only 50 us
<azonenberg_work> so waaaaay faster
<azonenberg_work> slg46620 is in between, 1.4 ms typical regardless of Vdd
<rqou> huh that's pretty slow
<azonenberg_work> yes, i think i know why
<rqou> sense amps? :P
<azonenberg_work> spartan6: 16-bit config datapath, very deep memory topology
<azonenberg_work> coolrunner: very wide and shallow config datapath (260 bits x 48 rows)
<azonenberg_work> Then greenpak is a bit different because they're using a standard TSMC 180nm NVM IP
<azonenberg_work> I suspect it's byte wide :p
<rqou> oh
<azonenberg_work> By 256 rows
<azonenberg_work> The physical die layout is 8 banks of 128 bits each, half above and half below a central spine
<azonenberg_work> Each bank is 32 cells wide by 5 bits high, i guess there's some parity or ecc or something in the array
<azonenberg_work> and of course, efuse is not exactly known for high speed compared to other kinds of memory
<rqou> hey, do you know what technology ice40 NVCM is?
<azonenberg_work> No, i have one on my bench but it isnt decapped
<rqou> it's not floating gates nor antifuse-in-vias
* azonenberg_work is stretched very thin
<azonenberg_work> Guessing silicide electromigration efuse
<azonenberg_work> But i have no data to support that
<azonenberg_work> Could also be SONOS
<azonenberg_work> but that's normally reprogrammable so i doubt it
<azonenberg_work> silicide electromigration can be done with few if any additional masks vs flash needs a lot
<azonenberg_work> so makes sense for cost optimized parts
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<rqou> lattice claims: "There are no ways known to Lattice Semiconductor to physically or electronically read the Non-
<rqou> Block RAM (BRAM) memory areas, or to otherwise extract digital information stored in NVCM
<rqou> Volatile Configuration Memory (NVCM), or to trace its path to the Configuration RAM (CRAM) or
<rqou> or CRAM memory areas."
<rqou> "The NVCM memory is programmed by slightly changing the insulating properties of the
<rqou> There is no change to the chemistry of the material itself - the same atoms remain in
<rqou> to changes in the chemical bonding in atomically sized regions of the gate dielectric.
<rqou> core transistor gate dielectric. These changes in conductivity are thought to occur due
<rqou> position."
<azonenberg_work> Huh
<azonenberg_work> Not familiar with any such memory, but NVM is not my area of expertise
<rqou> i bet it's still pwnable with the "tap the databus" technique that "dr. decap" seems to like a lot
<azonenberg_work> Yep
<rqou> actually seems to be more reliable than rom staining, just sayin' :P :P
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<azonenberg_work> lol
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<rqou> hmm "retro-compatible" nonvolatile-memory is ridiculously expensive
<rqou> unless you play some really crazy tricks, it has to be fram/mram
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<awygle> rqou: microsemi flash fpgas maybe? they claim to come up very quickly (essentially concurrent with the rail)
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<azonenberg_work> rqou: because nobody makes 5V silicon anymore :p
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<qu1j0t3> lol, seems you are right.
<azonenberg_work> these days i consider 3.3V "high voltage"
<azonenberg_work> and i mostly work at 1.8 for my IO
<qu1j0t3> :)
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<rqou> no, even ignoring the voltage problem, parallel-bus nonvolatile memory is weird :P
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<rqou> azonenberg_work: 8am classes suck :P
<azonenberg_work> Lol
<azonenberg_work> 8am "be at the client" sucks too
<azonenberg_work> especially when the customer is two time zones later than home
<azonenberg_work> i had to be at their office at 6am seattle time this morning
<azonenberg_work> after waking up at 4am seattle time
<azonenberg_work> :p
<rqou> sounds fun
<rqou> hey, do you think yosys formal verification can handle stable combinatorial loops? :P
<azonenberg_work> Nope
<azonenberg_work> I'd only use it for pure sequential stuff
<azonenberg_work> with a single clock
<rqou> hmm
<rqou> that won't work too well for my vaporware goal of "formally verified 6502 transistors to modern hdl"
<rqou> you need dynamic logic
<rqou> which can be turned into latches
<rqou> but now you need latches :P
<rqou> does anybody have any idea why visual 6502 is broken in just one of my browser profiles?
<rqou> clicking clicks in a random spot only in one of the profiles
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<rqou> whelp, i actually tested what happens if there is a logic loop when you try to use the yosys write_smt2 command, and it definitely fails
<rqou> it also cannot handle latches
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<azonenberg_work> rqou: poke to investigate the extract_reduce segfault i linked in ##yosys
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<rqou> azonenberg_work: er, "ERROR: Unimplemented counter clock source 6 (in COUNT14_0)"
<rqou> am i on the wrong version somehow?
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<azonenberg_work> Hmmm
<azonenberg_work> i should look into that
<azonenberg_work> doesnt seem to happen on mine, i'll check
<azonenberg_work> ... in the morning
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<openfpga-github> [yosys] azonenberg pushed 3 new commits to master: https://git.io/v5Ci0
<openfpga-github> yosys/master e346b87 Andrew Zonenberg: Merge branch 'master' of https://github.com/cliffordwolf/yosys
<openfpga-github> yosys/master c0034f5 Clifford Wolf: Merge pull request #397 from azonenberg/gpak-libfixes...
<openfpga-github> yosys/master 8530333 Clifford Wolf: Add {get,set}_src_attribute() methods on RTLIL::AttrObject
<openfpga-github> [yosys] azonenberg deleted gpak-libfixes at c314586: https://git.io/v5Ciu
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<azonenberg_work> rqou: ping
<rqou> pong
<azonenberg_work> What are your thoughts on rebasing azonenberg/yosys on top of current upstream?
<rqou> i wanted you to do that for a while :P
<azonenberg_work> Lol
<azonenberg_work> I'll try and do that when i get home from the client tonight then
<azonenberg_work> Do you know if anybody else is using our dev fork?
<rqou> idk
<rqou> the autobuilds build it
<rqou> but they do a clean checkout every time
<rqou> my personal policy has always been that dev forks can get rebased at any time without warning
<azonenberg_work> Ok, if we want to make that our policy then we can do that
<rqou> i don't know if you want to make that "our" policy
<rqou> e.g. i wouldn't do that on the openfpga repo
<azonenberg_work> well that is a more "stable" repo
<azonenberg_work> because it's the authoritative main repo of the project
<azonenberg_work> azonenberg/yosys is more of a prototyping-before-clifford-merges-it repo
<rqou> yeah
<azonenberg_work> So i think the policy should be, no rebasing on the primary repo
<azonenberg_work> But it's allowed on dev forks of upstream projects
<azonenberg_work> or on e.g. a private dev branch within openfpga
<rqou> yeah
<azonenberg_work> just not openfpga/master
<rqou> e.g. rqou/openfpga gets rebased all the time
<rqou> idk if you noticed :P
<azonenberg_work> I dont follow that fork much so no
<azonenberg_work> Anyway if we're in agreement i'll rebase it tonight
<azonenberg_work> Being 75 commits ahead of upstream with half of them being dummy merges is a bit much :p
<rqou> yeah, i don't get how people survive without rebase
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<azonenberg_work> ooook rebase time
<azonenberg_work> wish me luck
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<rqou> hey azonenberg_work guess what :P
<azonenberg_work> ?
<rqou> ROS (robot operating system) has reinvented Yet Another build system
<azonenberg_work> Lool
<rqou> aren't build systems _fun_? :P
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<pie_> oh god
<pie_> why ROS why
<pie_> doesnt ROS do a lot of weird sit
<rqou> it's fancy and academic?
<pie_> shit
<rqou> i don't think ros is any good either
<pie_> ive only tried to help my friend debug something once
<pie_> dont remember much about it exept for not being particularly impressed
<pie_> but it did seem to work overall
<pie_> or something
<azonenberg_work> rqou: ok this rebasing is going to be a giant pain in the neck
<azonenberg_work> do i really want to do this? :p
<rqou> wait why?
<rqou> git should automatically drop unneeded commits
<azonenberg_work> Thats not the issue
<azonenberg_work> the issue is, it's trying to apply my old unmerged changes and then undo them
<azonenberg_work> and i get merge conflicts each time
<azonenberg_work> Let me make a new branch and see what i can do...
<rqou> rebase -i and manually drop commits you don't like?
<azonenberg_work> i got a ways through that and it got painful
<azonenberg_work> Going to fix a few things so clifford can merge some of my other commits first
<azonenberg_work> All of the refactoring and cherrypicking is probably messing with things too
<rqou> oh damn 78 commits ahead
<rqou> yeeeah
<azonenberg_work> Lol :p
<azonenberg_work> You know what i might do?
<azonenberg_work> First, fix some of my pending changes so clifford can merge my other refactoring
<rqou> just take clifford's master and cherry-pick unmerged changes?
<azonenberg_work> Yeah
<azonenberg_work> basically that
<azonenberg_work> Take his master, merge all of my feature branches, then cherry-pick whatever is left
<azonenberg_work> and call that my new master
<azonenberg_work> i think it'll be easier than trying to retcon all of my past history
<rqou> yeah
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<azonenberg_work> grr this is going to be a pain in the butt either way
<azonenberg_work> let me try rebasing again...
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<openfpga-github> [yosys] azonenberg force-pushed master from e346b87 to c1785f4: https://git.io/v5WjG
<openfpga-github> yosys/master 2dbff07 Andrew Zonenberg: Fixed undeclared "count" in GP_COUNT14_ADV
<openfpga-github> yosys/master d89939c Andrew Zonenberg: Fixed typo in error message
<openfpga-github> yosys/master b5deee6 Andrew Zonenberg: Fixed undeclared "count" in GP_COUNT8_ADV
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<azonenberg_work> I think it worked
<rqou> we're still 30 commits ahead?
<rqou> have you made sure we haven't dropped anything btw?
<rqou> azonenberg_work: you need to drop recover_reduce
<rqou> also, despite clifford not liking it, the PR for TFFs is missing a commit
<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v5Wjh
<openfpga-github> yosys/master e90eb0d Andrew Zonenberg: extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
<openfpga-github> [yosys] azonenberg pushed 1 new commit to counter-extraction: https://git.io/v5lev
<openfpga-github> yosys/counter-extraction 634f18b Andrew Zonenberg: extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
<azonenberg_work> oh let me fix that
<azonenberg_work> i'm not gonna rebase recover_reduce out, ok? just delete it?
<azonenberg_work> it'll get squashed whenever we fully merge with upstream
<rqou> yeah
<rqou> wait
<rqou> recover_reduce is already upstream
<openfpga-github> [yosys] azonenberg pushed 1 new commit to recover_tff: https://git.io/v5len
<openfpga-github> yosys/recover_tff 5fd9c2a Robert Ou: Fix bug loading libraries when they are already loaded
<azonenberg_work> Yes. but called extract_reduce
<azonenberg_work> so if we have recover as well that has to get removed
<azonenberg_work> no we're good
<azonenberg_work> so are we OK now?
<azonenberg_work> I have a full clone of our old history if we have to pull any work out of it
<azonenberg_work> But i think i got everything
<rqou> i thought clifford renamed recover to extract (so we can drop recover)
<azonenberg_work> Do we have recover in our current version?
<azonenberg_work> i thought i removed recover when extract got merged to mainline
<azonenberg_work> there might be an add-and-delete commit in our history
<azonenberg_work> but is it worth editing that out?
<azonenberg_work> it turns into a nop so when upstream merges the history will be sane
<rqou> ooh wait
<rqou> i might be confused
<rqou> i see a commit adding it, but i think you remove it somewhere
<azonenberg_work> Yeah
<azonenberg_work> I removed it when clifford merged it to upstream
<azonenberg_work> somehow it didn't auto-remove when the merge happened
<azonenberg_work> and it still thinks it's a new commit
<rqou> manually squash?
<openfpga-github> yosys/recover_adder ad975af Andrew Zonenberg: Merge branch 'master' of https://github.com/cliffordwolf/yosys into recover_adder
<openfpga-github> [yosys] azonenberg pushed 1 new commit to recover_adder: https://git.io/v5leK
<azonenberg_work> is it worth it?
<rqou> eh, maybe not
<azonenberg_work> It's not 78 commits ahead now
<azonenberg_work> so this is progress :p
<azonenberg_work> And we *have* been doing a lot of stuff
<openfpga-github> [yosys] azonenberg pushed 2 new commits to recover_tff: https://git.io/v5le7
<openfpga-github> yosys/recover_tff 6b7c585 Andrew Zonenberg: Merge branch 'recover_tff' of github.com:azonenberg/yosys into recover_tff
<openfpga-github> yosys/recover_tff 9114474 Andrew Zonenberg: Merge branch 'master' of https://github.com/cliffordwolf/yosys into recover_tff
<openfpga-github> [yosys] azonenberg pushed 1 new commit to counter-extraction: https://git.io/v5leF
<openfpga-github> yosys/counter-extraction 0675410 Andrew Zonenberg: Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction
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<azonenberg_work> rqou: ok so i think i'm going to work on optimizing counters in extract_counters now
<azonenberg_work> Then probably figure out how to optimize counters that don't techmap to hard IP
<azonenberg_work> by extracting them in a separate step, followed by techmapping back to generic RTL