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<openfpga-github> [yosys] azonenberg pushed 3 new commits to master: https://git.io/v5ZiG
<openfpga-github> yosys/master 8112d69 Andrew Zonenberg: Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.
<openfpga-github> yosys/master f218a6c Andrew Zonenberg: Refactored extract_counter to be generic vs GreenPAK specific
<openfpga-github> yosys/master b3aa698 Andrew Zonenberg: Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass
<azonenberg_work> rqou: sooo it looks like my counter optimization pass is basically going to involve extracting counters then re-techmapping them, lol
<azonenberg_work> Should be easy enouhg
<azonenberg_work> enough*
<openfpga-github> [yosys] azonenberg created counter-extraction (+3 new commits): https://git.io/v5Zi0
<openfpga-github> yosys/counter-extraction 3fc1b9f Andrew Zonenberg: Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.
<openfpga-github> yosys/counter-extraction 46b01f0 Andrew Zonenberg: Refactored extract_counter to be generic vs GreenPAK specific
<openfpga-github> yosys/counter-extraction b5c1563 Andrew Zonenberg: Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass
<azonenberg_work> In particular, what i need to do is
<azonenberg_work> * make extract_counter support more counter configurations (eventually)
<azonenberg_work> * make extract_tff_counter work, and map chains of TFFs to $__COUNT_ cells
<azonenberg_work> * add an optimization step to extract_counter that detects counters with more bits than necessary and shrinks them
<azonenberg_work> * create a script pass that runs extract_counter followed by techmapping of a generic counter model
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<cr1901_modern> https://github.com/RHSResearchLLC/NanoEVB-X1 Wonderful project, but... why aren't the kicad files open sourced?
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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/v5csX
<openfpga-github> openfpga/master 0201eb0 Andrew Zonenberg: Added RedundantFF test
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<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v5cnS
<openfpga-github> yosys/master 8b05822 Andrew Zonenberg: Refactoring: moved modules still in cells_sim to cells_sim_wip
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<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/v5c2p
<openfpga-github> yosys/master a596413 Andrew Zonenberg: Added blackbox $__COUNT_ cell model
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<rqou> azonenberg_work: btw, we really really need XORs in the cpld synth flow
<rqou> a simple 8+8->8 bit adder uses a ludicrous 300+ p-terms otherwise
<rqou> we should start figuring out how we're going to annoy alanmi :P
<azonenberg_work> lol
<rqou> we also need to figure out p-term sharing
<rqou> but it seems that's not as useful as i expected
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<azonenberg_work> How's the blinky netlist look when you "show" it?
<azonenberg_work> i think its pretty good progress
<rqou> i haven't tried yet
<rqou> hey azonenberg_work, do you think ice40 hx8k has enough LUTs to make use of hyperram?
<azonenberg_work> I'll let you know how big my controller for artix is when i write it :)
<rqou> hyperram's small number of pins looks pretty neat actually
<rqou> too bad the capacity is small
<rqou> argh
<rqou> hyperram still has the "center aligned when you send, edge aligned when you read" thing
<azonenberg_work> Is that an issue? I thought ice40 had a PLL
<azonenberg_work> you should easily be able to generate a phase shifted write clock, no?
<rqou> i'm not sure, but reading will definitely be "fun"
<rqou> there's no IDELAY
<azonenberg_work> Yeah you will likely have to downclock a bit and hope for the best
<azonenberg_work> For my 667 MT/s core on artix i was planning to do full data eye calibation