<awygle_m>
So what exactly is abc anyway? Besides huge, ugly and "something to do with AIGs"?
<rqou>
afaict it's "AIG algorithm dumping ground"
<rqou>
plus some non-AIG algorithms like retiming
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
pie_ has quit [Ping timeout: 240 seconds]
enriq has joined ##openfpga
awygle_m has quit [Ping timeout: 240 seconds]
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
<awygle>
been a while since i've had to superglue an allen wrench into a screw. guess that's what i get for putting shelves together with a drill
enriq has joined ##openfpga
theMagnumOrange has joined ##openfpga
<rqou>
so apparently accidentally playing a pdf in vlc can crash the entire gpu driver
<rqou>
quality
GenTooMan has quit [Quit: Leaving]
awygle has quit [Quit: Page closed]
awygle has joined ##openfpga
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
enriq has joined ##openfpga
enriq has quit [Client Quit]
<azonenberg_work>
TIL this little game i've been playing on my 3DS is actually a fairly well studied NP-complete problem https://en.wikipedia.org/wiki/Nonogram
<azonenberg_work>
i mean when you think about it, it makes sense that it reduces to SAT
<rqou>
but then everything reduces to SAT :P
<azonenberg_work>
There are obvious heuristics (detailed on that page) that run in polynomial time
<rqou>
but this is true for many np-complete problems as well
<azonenberg_work>
I think O(mn) for N clues in a given row and M cells
<azonenberg_work>
But they only get you so far
<azonenberg_work>
once you start entering the backtracking/searching for contradictions phase the NP-completeness becomes obvious
<rqou>
hey azonenberg_work does xbpar return immediately if a legal placement is found?
<azonenberg_work>
No
<azonenberg_work>
It continues trying to optimize the cost function until some number (I forget what) of steps with no improvement, or the temperature hits zero
<azonenberg_work>
Right now it primarily tries to minimize the number of unroutable nets and the number of nets crossing the central spine in greenpak
<azonenberg_work>
But it will eventually take the timing score of the design into account too
<rqou>
ooh i forgot about the central spine crossing minimization
<rqou>
because xc2 doesn't have that
<rqou>
hmm but even with that requirement, since there is currently no timing information, it should immediately return once it has found a legal placement for everything (including spine congestion), right?
<azonenberg_work>
If the cost metric hits zero, it returns immediately
<azonenberg_work>
Otherwise it keeps trying to improve
<azonenberg_work>
until it plateaus
<rqou>
but in your current actual implementation, the cost should hit zero once a valid placement is found, right?
<rqou>
the reason i ask is
<azonenberg_work>
It does not
<azonenberg_work>
there is always a cost for crossing the central spine
<azonenberg_work>
in greenpak
<rqou>
ah
<azonenberg_work>
So unless your design is two independent subgraphs
<rqou>
anyways, the reason i ask is because in my shitty xc2 implementation
<azonenberg_work>
which each fit in one half of the device
<rqou>
the cost will hit 0 immediately when a legal placement is found
<azonenberg_work>
it will continue at least N iterations after it reaches the optimal placement
<azonenberg_work>
b/c it doesnt know it's optimal :p
<rqou>
and i noticed that it wasn't really "annealing" at all
<azonenberg_work>
Well zero is considered an optimal placement
<rqou>
so i went and reviewed some lecture notes on CSPs
<azonenberg_work>
So there is no optimization possible
<rqou>
and it turns out what i essentially implemented is called "min-conflicts"
<azonenberg_work>
Your cost function has to be more complex :p
<azonenberg_work>
i.e. include timing data
<rqou>
which actually works amazingly well, unless you hit a particular range of # constraints / # variables
<azonenberg_work>
and probably area as well (for when we start doing resource sharing)
<rqou>
which i guess i've been lucky and haven't hit :P :P
<azonenberg_work>
lol
<azonenberg_work>
My gp4par code is actually annealing
<azonenberg_work>
combined with a bit of random walk :p
<azonenberg_work>
i can probably improve it, but it seems to work fairly well
<rqou>
my algorithm is basically this:
<azonenberg_work>
ideally i want to do an analytic placer though
<rqou>
Algorithm: While not solved,
<rqou>
Variable selection: randomly select any conflicted variable
<rqou>
Choose a value that violates the fewest constraints
<rqou>
Value selection: min-conflicts heuristic:
<azonenberg_work>
So are you not using the xbpar par engine?
<rqou>
it is
<azonenberg_work>
because it's supposed to do a lot of this for you
<azonenberg_work>
all you have to do is define the set of nodes that are not in optimal placements
<rqou>
not the conflicted variable selection
<azonenberg_work>
the overall cost function
<rqou>
yeah that
<azonenberg_work>
And then pick a node you want to consider moving
<rqou>
my cost function is shit, so xbpar doesn't learn anything from that
<azonenberg_work>
Lol :p
<azonenberg_work>
thats your problem
<rqou>
which is how the old "only works 10% of the time" issue came up
<rqou>
anyways, GetNewPlacementForNode is implemented in each engine, not in the common code
<azonenberg_work>
Yes
<azonenberg_work>
in greenpak i just pick a legal placement at random :p
<rqou>
so when i fixed my code, i made GetNewPlacementForNode return a placement that minimized the number of unroutable edges
<azonenberg_work>
Coolrunner has a more complex structure so its less trivial
<azonenberg_work>
You don't want to automatically minimize
<azonenberg_work>
thats where the randomness in annealing comes in
<azonenberg_work>
You move downward, but occasionally not
<azonenberg_work>
To avoid getting stuck in a local minimum
<rqou>
so here's the thing
<rqou>
without a timing score and with only a "legal/not legal" cost function
azonenberg_work has quit [Ping timeout: 240 seconds]
teepee has quit [Ping timeout: 258 seconds]
teepee has joined ##openfpga
ZipCPU|Laptop has quit [Ping timeout: 248 seconds]
teepee has quit [Ping timeout: 248 seconds]
teepee has joined ##openfpga
teepee has quit [Ping timeout: 252 seconds]
teepee has joined ##openfpga
teepee has quit [Ping timeout: 240 seconds]
teepee has joined ##openfpga
teepee has quit [Ping timeout: 258 seconds]
teepee has joined ##openfpga
cr1901_modern has quit [Read error: Connection reset by peer]
cr1901_modern1 has joined ##openfpga
pie__ has quit [Ping timeout: 248 seconds]
m_t has joined ##openfpga
m_t has quit [Remote host closed the connection]
m_t_ has joined ##openfpga
teepee has quit [Ping timeout: 248 seconds]
teepee has joined ##openfpga
teepee has quit [Ping timeout: 252 seconds]
teepee has joined ##openfpga
azonenberg_work1 has quit [Ping timeout: 248 seconds]
m_t_ has quit [Quit: Leaving]
eduardo_ has quit [Remote host closed the connection]
azonenberg_work has joined ##openfpga
enriq has joined ##openfpga
indy has quit [Ping timeout: 240 seconds]
test123456 has joined ##openfpga
indy has joined ##openfpga
<awygle>
Huh, AIGs are cool I guess. They basically serve as a canonical representation, and then you can do graph reductions and things to make them smol? Is that ~right?
<awygle>
Whether that's the best way or even a good way to do so of course...
<awygle>
shapr: yep
<shapr>
I've seen this pattern of program -> circuit -> logic minimization -> reimplement in .. four? different research areas. Is there a name for that process?
<awygle>
Interesting. I'm too ignorant to see an obvious advantage though, would have to read much more carefully
<azonenberg_work>
shapr: Its nice to understand all the pieces but if you specifically want to get started by REing FPGA structures
<azonenberg_work>
you don't necessarily have to understand all of the details of synthesis to reverse the bitstream format
<azonenberg_work>
I'd focus on studying the low level details of the FPGA microarchitecture and bitstream first
<azonenberg_work>
the more you know the better, but you can make useful contributions to the project before you understand all the synthesis stuff
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
<shapr>
yeah, true
cr1901_modern1 is now known as cr1901_modern
enriq has joined ##openfpga
Hootch has quit [Quit: Leaving]
azonenberg_work has quit [Ping timeout: 248 seconds]
azonenberg_work has joined ##openfpga
digshadow1 has joined ##openfpga
digshadow has quit [Quit: Leaving.]
grantsmith has joined ##openfpga
m_t has joined ##openfpga
<rqou>
azonenberg_work: so i've been trying to reformulate PAR as a CSP, and apparently the part i'm having trouble with isn't the CSP part but the "is this partial assignment legal" part, which is just GI
<rqou>
i totally deserve my CS degree :P
<shapr>
GI?
<awygle>
Graph isomorphism
<rqou>
graph isomorphism
<shapr>
oh!
<rqou>
lol apparently berkeley and/or other "$FANCY_SCHOOLS" all have this silly shared jargon
<awygle>
Na I'm just a working engineer, meaning I spend 50% of my day making up acronyms and the other 50% guessing other people's :-P
<rqou>
awygle: what about everybody's favorite acronym, IP? :P
azonenberg_work has quit [Ping timeout: 248 seconds]
<rqou>
need to talk to your IP lawyer about your new invention related to IP packets :P
<shapr>
totally not ambiguous
<awygle>
Yeah but Intellectual Property isn't an actual legal term :-P
<rqou>
fine :P
<rqou>
what's your favorite stupid acronym?
<awygle>
That feel when the PDF link to "Synthesis with external don't-cares using Shannon entropy and Craig interpolation" is purple... I have no memory of this
<rqou>
oh i just remembered a fun not-even-an-acronym: "I$" and "D$"
<rqou>
awygle should know what this means :P
<rqou>
(afaik this is also a $FANCY_SCHOOL thing)
<awygle>
Instruction and data cache.
<awygle>
I didn't learn it at cal though
<rqou>
oh wtf something i _just_ discovered
<rqou>
cory199 is now always locked
<rqou>
must be "security concerns"
<shapr>
I went back to school to get a bachelor's degree after a 15 years career, that was a weird experience.
<rqou>
also, berkeley eecs finally got rid of their unsecured printers that you could print to from anywhere :(
<rqou>
thanks weev
<shapr>
ha, my university had that
<awygle>
I don't remember which one is 199. I do remember the occasional skinhead mailer sitting in the soda printer though
<rqou>
lol that isn't a new thing?
<awygle>
Sadly no
<shapr>
I went to university of north alabama, when I arrived the head of CS thought Fortran jumped the shark with Fortran95. When I left she was teaching Haskell and Python. I made a bunch of waves, but it turned out well.
<rqou>
i just mostly remember seeing pdfs printed as text because some freshmen couldn't get lp to work on the solaris boxes
<shapr>
ok that's amusingy
<shapr>
I persuaded the math profs to give a 5% grade bonus to any homework submitted in LaTeX
<shapr>
I started a robotics club and a makerspace, both of which failed :-(
<rqou>
also, berkeley eecs has been killing the color printers :(
<shapr>
I kinda wish I'd gone to a big name university.
<rqou>
awygle: phaser in soda is gone because apparently zero noobs knew how to use it and anybody who did know how to use it abused it a lot to print fliers or whatever
<awygle>
To be fair, Unix printing is a tire fire. Have you ever noticed how some things just decide to be hard even though they really shouldn't be? Audio is another good one.
<rqou>
yeah true
<shapr>
I haven't seen printing work well on anything.
<awygle>
(build systems are fundamentally hard though :-P)
<shapr>
and you have so many to choose from!
<shapr>
make? cmake? ant? shake?
<rqou>
splash? :P :P
<awygle>
I wonder at what resolution you could print a bitmap as pixels/dots and your eye wouldn't be able to tell the difference.
<shapr>
yeah, azonenberg's build system
<rqou>
awygle: now you're thinking like apple! :P :P
<shapr>
awygle: I got 300 normal pages of text on one page at 1pt font with the margins pushed out as far as the Laserjet 4P would do
<awygle>
Well postscript is a big part of the problem to my way of thinking
<shapr>
I think I had to do 1200DPI printing to keep it readable with a magnifying glass
<shapr>
I really like postscript, it's a fun language to code!
<awygle>
Anyway. Not relevant to either fpgas or the paying job I'm supposed to be doing right now. Later
<shapr>
very few printers that do postscript these days though
<shapr>
yeah, I could stand to do more C# code :-|
<awygle>
Hey, is anybody working on any open source SystemC stuff?
<awygle>
I don't particularly want it, just curious
<rqou>
well, you should join the bikeshed anyways :P
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
enriq has joined ##openfpga
azonenberg_work has joined ##openfpga
<azonenberg_work>
Checking a GI in polynomial time is easy
<awygle>
Lol. My going in position is don't fight the standard. But I haven't thought about it much.
<azonenberg_work>
what did i miss?
<grantsmith>
now i want to go back to university :(
<grantsmith>
thanks a lot guys
<grantsmith>
i will live vicariously through my children
<rqou>
azonenberg_work: um, GI is not proven to be in P
<grantsmith>
shapr, i too enjoyed postscript programming.. the RPN-ness of it all reminded me of programming in forth
pie_ has joined ##openfpga
<rqou>
huh, GI is in P for graphs with bounded degree (which we have)
<shapr>
grantsmith: I got the same thrill from writing Joy
<awygle>
Well, and checking it is in P, surely
<awygle>
Finding a surprising number of papers on MIGs, might be worth looking at in more depth (seems to be A Thing)
<rqou>
oh yeah, pointfree was looking into that a while back
<rqou>
i saw one paper that said that it's even better for fitting things into carry chains
<azonenberg_work>
rqou: Checking a GI
<rqou>
oh right
<azonenberg_work>
i.e. given an embedding of one graph into another
<rqou>
anyways, i know it's polynomial time
<azonenberg_work>
you can easily check in O(G+E)
<rqou>
i just can't get the code to not have bugs :P
<azonenberg_work>
whether this is an isomorphism or not
<azonenberg_work>
You just cant always *generate* it in polynomial time
<azonenberg_work>
Which proves, trivially, that GI is in NP
<grantsmith>
shapr, wow.. was Joy compiled or interpreted ?
<rqou>
right, but right now i just have a "debugging" problem
<rqou>
my favorite :P
<shapr>
grantsmith: interpreted
<grantsmith>
shapr, does it still exist ? I can't seem to find anything
<grantsmith>
like.. a linux interpreter for it ?
<pointfree>
shapr, grantsmith: Forthy languages are usually interactively compiled. Compiled vs interpreted is kind of a false dichotomy.
<azonenberg_work>
rqou: is debugging in NP?
<azonenberg_work>
:P
<rqou>
debugging is undecidable :P
<azonenberg_work>
actually pretty sure it trivially reduces to the halting problem
<azonenberg_work>
So yes, undecidable
<shapr>
grantsmith: Sadly, the primary author (Manfred von Thun) is deceased, but there's still much you can find. There's also the #concatenative irc channel for that flavor of proglangs
<grantsmith>
pointfree, i see.. the only reason i ever experienced forth was by being subjected to it via a "game development" package on a Sinclair ZX Spectrum
<shapr>
I did love my Timex Sinclair :-)
<rqou>
i was expecting a "game development" "package" in a "java sandbox environment" :P
<shapr>
grantsmith: do you do FPGAs for a living?
<rqou>
(cue inbound drama)
<pointfree>
grantsmith: The Joy stuff was on a .edu website which meant it got deleted (like a lot of .edu stuff). But fortunately it was all backed up.
<grantsmith>
shapr, i do not. I am trying to expand my horizons :p
<azonenberg_work>
7 series, even the low-end stuff like the new spartan-7 coming out soon, is based on the virtex microarchitecture
<grantsmith>
wow, the Pro Edition of Quartus Prime is NOT CHEAP
<azonenberg_work>
with a nice clean columnar layout
<azonenberg_work>
grantsmith: Ditto for ise and vivado
<azonenberg_work>
But keep in mind, you normally would use those to write software for $2000+ FPGAs
<rqou>
but lmcrypt is "well-studied" :P
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
<azonenberg_work>
Lol
<shapr>
ha, that's a good reason
enriq has joined ##openfpga
<shapr>
well, too bad the novena has the spartan6
<azonenberg_work>
I mean we can look at it, but its not a high priority
<azonenberg_work>
it does have some uses
<shapr>
oh well, off to teach wearable arduino coding
<rqou>
btw, the actual highest priority right now is an analytic PAR
<azonenberg_work>
in particular, the static power per logic capacity is way less than the 28nm parts
<rqou>
not RE
<azonenberg_work>
Yeah
<azonenberg_work>
We can test it on ice40
<azonenberg_work>
That would put us leaps and bounds ahead of any other public fpga work
<rqou>
once someone goes and explains better how ice40's routing works :P
<rqou>
*hint* *hint* rlutz :P :P
<azonenberg_work>
even VPR, the de facto standard for this kind of stuff, is annealing based to some degree
enriq has quit [Client Quit]
enriq has joined ##openfpga
<awygle>
I've been thinking about this, obviously. What would your vision for testing be, assuming something comes to exist?
<rqou>
ice40?
<rqou>
a hypothetical upscaled ice40? (is this possible?)
<awygle>
Yes, I can fake an upscale ice40 pretty easily
<awygle>
(IIUC)
<azonenberg_work>
I would start with ice40 and then try to move to an artix7
<azonenberg_work>
We can skip a lot of the RE if only doing a placer and not a router
<azonenberg_work>
basically emit verilog with LOC constraints on each primitive
<azonenberg_work>
then the xilinx par will degenerate to a router
<azonenberg_work>
and bitstream generator
<azonenberg_work>
So this would let us test placement on, say, a 7a100t without needing to RE the full bitstream yet
<azonenberg_work>
in parallel with that we could RE the bitstream
<azonenberg_work>
so that ideally by the time we're ready to write a router, we'll have enough bitstream reversed to get at least LUT/FF/BRAM/IO netlists working
<rqou>
can you actually LOC everything in artix7?
<rqou>
in coolrunner-ii you can't
<azonenberg_work>
what can you not loc in coolrunner?
<azonenberg_work>
i know you dont get control over the PLA packing
<rqou>
individual and/or terms in the PLA
<azonenberg_work>
ah yes
<rqou>
which isn't super useful
enriq has quit [Ping timeout: 240 seconds]
<rqou>
unless you're doing some weird "make it analog" hack
<azonenberg_work>
in FPGAs you can use the BEL constraint plusLOC
<azonenberg_work>
to force a given LUT to say SLICE_X0Y3 BLUT
<rqou>
til about BEL
<azonenberg_work>
awygle: thoughts?
<rqou>
welcome to my life: shit at hdl, shit at coding, and yet working on EDA
<rqou>
:P
enriq has joined ##openfpga
<azonenberg_work>
basically just serialize the netlist you'd normally use for feeding to the router
<azonenberg_work>
but spit out verilog instead
<azonenberg_work>
and let par do the rest
<azonenberg_work>
Then we can have fun comparing run time and QoR to ISE and Vivado on the same netlist
<azonenberg_work>
we can synthesize with yosys to raw lut/dff primitives, to take xst out of the equation
<azonenberg_work>
and basically compare ise map and vivado par directly to our own analytic placer without the rest of the toolchain being different
<azonenberg_work>
using this approach we can also use xilinx timing analysis on our netlists
<azonenberg_work>
to accurately compare Fmax against the official toolchain
<rqou>
xst is surprisingly good considering that afaik it's built on ancient techniques
<azonenberg_work>
Yeah but i mean
<rqou>
yosys (abc?) is great at combinatorial optimization but _sucks_ at handling processes
<azonenberg_work>
Yeeeeah
<azonenberg_work>
But improving synthesis is a separate battle
<azonenberg_work>
In order to do a properly controlled experiment i want to use the same post-synth netlist
<azonenberg_work>
and the same router
<azonenberg_work>
and only change the placer
<azonenberg_work>
Then as a separate stage we can compare yosys to xst and vivado synthesis using the same backend (which may be ours or theirs)
<rqou>
no link right now, but there's a paper where someone tried that by being really good at tcl+vivado
enriq has quit [Client Quit]
<rqou>
but they didn't write a real placer, just a "framework" and a random placer
<azonenberg_work>
Yeah
<azonenberg_work>
Anyway, i think that should be our longer term roadmap for the analytic placer
<azonenberg_work>
have xc7a100t be the target after ice40
<rqou>
why not 50t?
enriq has joined ##openfpga
<rqou>
er, "15t"
<azonenberg_work>
Because it's bigger :p
<rqou>
lol
<awygle>
Okay, that all sounds reasonable. The idea of forcing LOC on Xilinx to use their router didn't occur to me
<rqou>
so is "15t"
<azonenberg_work>
we'd be testing scalability at that point
<azonenberg_work>
I want something big but affordable
<rqou>
isn't 100t $300?
<azonenberg_work>
no
<azonenberg_work>
$100ish
<azonenberg_work>
and we'd be using the xilinx backend so the bitstreams should always be safe
<rqou>
hmm, what was i looking at that was $300-ish?
<azonenberg_work>
i..e no risk of killing the device
<rqou>
must have been a kintex
<awygle>
How hard would it be to formally prove that the pre- and post- placement netlists are equivalent?
<azonenberg_work>
maybe the whole board is 300 if its a partiuclar device
<azonenberg_work>
awygle: Easy, if you propagate instance names
<azonenberg_work>
bitstream to netlist is harder
<awygle>
Fast but wrong is less useful than slow but correct lol
<azonenberg_work>
but netlist to netlist isomorphism is almost trivial as long as you don't do optimization during placement
<rqou>
eh, just make it wrong a small enough percentage of the time
<azonenberg_work>
if you replicate drivers, etc then it'd reduce to SAT and we could use yosys's formal equivalence checkers
<rqou>
now you're thinking like a CS major :P
<awygle>
Okay, should be easy enough
<rqou>
azonenberg_work: oh now you're using SAT. but a SAT-based PAR is bad? :P :P
<azonenberg_work>
sat for debugging a par
<awygle>
Lulz
<azonenberg_work>
is very different than sat for implementing a par :p
<azonenberg_work>
BTW
<azonenberg_work>
once we do have more bitstreams RE'd
<rqou>
a framework?
<azonenberg_work>
i want to be able to do LVS checking of bitfile back to hdl
<rqou>
btw i was thinking about why xc2bit has so many special cases
<rqou>
it's not a great reason
<azonenberg_work>
full fdormal equiv end to end
<rqou>
basically it was just to insert linebreaks in the .jed
<azonenberg_work>
loool
<rqou>
but it's now possible to do that in a much less ugly way thanks to later refactoring
<awygle>
LVS? Layout vs schematic?
<azonenberg_work>
Yes
<awygle>
I would guess that'd have to assume your "turn in a bit file into a netlist" and your "turn a netlist into a bit file" tools are correct
<azonenberg_work>
Basically formally proving techmap + par didnt chane the logical semantics
<azonenberg_work>
And yes
<awygle>
No real way to prove them without a public spec
<azonenberg_work>
But we can verify map and par
<azonenberg_work>
Better than nothing
<awygle>
Mhm
<azonenberg_work>
ASIC LVS has to trust the extraction tool too
<awygle>
That's a good problem for someone formal-y, to get started on that work with XC2, GP4, and ice40
<azonenberg_work>
I think i have what i need to do it now
<azonenberg_work>
my bit to net tool plus yosys $equiv
<azonenberg_work>
the only missing part is a map file
pie_ has quit [Remote host closed the connection]
<azonenberg_work>
you need to know what pins etc di what
<azonenberg_work>
do*
pie_ has joined ##openfpga
<azonenberg_work>
also unsure of how to handle hard ip and multiple clocks / internally generated clocks
<rqou>
you know, yosys has been surprisingly good at not having "wrong answer" bugs
teepee has quit [Ping timeout: 240 seconds]
pie_ has quit [Read error: Connection reset by peer]
pie_ has joined ##openfpga
<awygle>
Oh yeah that was another thing I was going to solicit thoughts on. Placement for hard IP. Put it in the legalization step, you think? Or try to be more clever?
<awygle>
Analytic feels like it doesn't map super well to hard IP, unlike annealing
GenTooMan has joined ##openfpga
teepee has joined ##openfpga
<rqou>
dumb idea: given sufficiently few hard IP, use "cutset conditioning" --> assign all possible placements of hard ip and then run the normal analytic placement for the rest
<rqou>
and pick the best one :P
<awygle>
Way to implicitly increase the performance requirement by >= 1 order of magnitude :-P
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
<awygle>
Slightly less dumb idea: random preplacement of hard IP, rerun if the placement fails.
<rqou>
is that actually better?
<rqou>
you can abort my approach early if the result is "good enough"
<azonenberg_work>
Is there any reason why hard ip cant be treated like luts or other primitives?
<awygle>
Pretty sure your way is O(N!)
<azonenberg_work>
you're just placing cells
<azonenberg_work>
why do you care what they do?
<awygle>
That is essentially the "do it in legalization" approach I mentioned above. You're legalizing to a smaller, sparser grid for those cells.
<azonenberg_work>
ah, yeah
<azonenberg_work>
That is probably the best option
<azonenberg_work>
i mean, not all luts can go in every place either
<azonenberg_work>
i.e. a SRLC32E or RAM32x1S
<azonenberg_work>
can only go in a SLICEM
<rqou>
my approach is only O(N!) where N is the number of hard IP
<rqou>
not the total sites
<azonenberg_work>
rqou: ok, now imagine "hard IP" = block rams
<rqou>
i think yours is too in the worst case
<azonenberg_work>
and you have 750 of them
<azonenberg_work>
in a 7a200t
<rqou>
legalization sounds better :P
<azonenberg_work>
lol
<awygle>
rqou: yes. Mine is O(infinity) in the worst case lol
<rqou>
no it isn't
<rqou>
it's still bounded by the total cells in the device
<rqou>
:P
<awygle>
Only if I'm remembering what I've tried, which I did not specify :-P
<awygle>
Anyway. Legalization yay. That's the easiest way (that isn't gratuitously bad)
<rqou>
oh goddammit
<rqou>
##openfpga, the shitty CS channel :P
<azonenberg_work>
lol
enriq has joined ##openfpga
* azonenberg_work
is excited to have this discussion move to a whiteboard in meatspace
fouric1 has joined ##openfpga
<awygle>
Says mister "I can't solve graph isomorphism" :-P
<rqou>
lolol
<rqou>
how many berkeley EECS majors does it take to write a PAR? :P
<whitequark>
lol
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
<awygle>
azonenberg_work, are you back yet?
<azonenberg_work>
No
<azonenberg_work>
My flight leaves noon chicago time tomorrow
<azonenberg_work>
arrive SEA around 18:00
<awygle>
Ah, well done missing all the smoke
<awygle>
Well... Most of the smoke.
<azonenberg_work>
Lol
<azonenberg_work>
yeah it was raining ashes on bainbridge the other day
<azonenberg_work>
$WIFE sent me a pic
<awygle>
Redmond too. I stopped biking to work for the week.
* azonenberg_work
would have just worn a N100 respirator and powered through it
<azonenberg_work>
That's what i did during the last smoke-out
<rqou>
biking with a respirator?
<awygle>
I am not nearly as well stocked for the apocalypse as you are
<azonenberg_work>
It's a little harder to breathe through the filter, but not enough to matter unless you're riding really fast uphill etc
<azonenberg_work>
for casual riding on flat ground you can get plenty of air
<azonenberg_work>
awygle: lol
<awygle>
I borrowed an almost certainly useless face mask
<rqou>
what was the type of respirator whitequark was recommending?
<rqou>
is that what you have azonenberg_work?
* azonenberg_work
has one for himself and one for $WIFE in the garage unopened, plus one more on the bike that was used a few times during the last smoke incident but is probably still OK for a bit more
<awygle>
Although I could have spent way less on a respirator than one tank of gas for the shitty truck, so on balance...
<grantsmith>
azonenberg, on behalf of Oregon I apologize
<awygle>
That amazon page leads me to the inevitable conclusion that azonenberg_work has an Amazon subscription to these respirators
<azonenberg_work>
Lol, i dont
<grantsmith>
that fire was started by some clueless kid shooting off fireworks
<azonenberg_work>
I actually didn't keep them on hand
<azonenberg_work>
i got them after the last smoke cloud arrived
<awygle>
Don't disrespect my headcanon :-P
<rqou>
wait, is N100 for particulates only?
<azonenberg_work>
They're not bad to have for construction etc work, plus if rainier ever blows its top then it will be handy:p
<azonenberg_work>
Wildfire is a secondary benefit
<azonenberg_work>
rqou: N100 is for non-oil-based particulates
<azonenberg_work>
P100 is N100 but oil resistant
<rqou>
ah
<azonenberg_work>
then typically for solvent vapors etc you'd wear a half-face or full-face respirator with side mounted cartridges
<grantsmith>
i think N100 is basically just an activated carbon layer
<azonenberg_work>
No
<azonenberg_work>
It's not carbon at all, it's a fibrous filter of some sort
<rqou>
iirc whitequark was recommending ABEK for chemistry work
<azonenberg_work>
it does nothing to vapors
<grantsmith>
i stand corrected
<azonenberg_work>
Typical solvent crtridges will include a N95 or N100 pre-filter over them
<azonenberg_work>
just so that you dont clog the activated carbon up with particulates
<azonenberg_work>
Such masks will protect against particulates as well as whatever fumes the carbon filter was designed for (they often are treated with specific chemicals to neutralize particular vapors etc)
<azonenberg_work>
awygle: i'm well stocked in some kinds of emergency/survival gear as a result of being in SAR, but typically wilderness rescues don't involve getting gassed
<azonenberg_work>
So respirators weren't on my shopping list :p
<rqou>
why don't you have a big jug of WFNA and HF yet? :P
<azonenberg_work>
Because i dont have a fume hood to use it in
<rqou>
(separately, of course :P :P )
<azonenberg_work>
I have 3% HF but havent used it since i moved
<rqou>
do what whitequark does and don't use a fume hood at all
<azonenberg_work>
No white fuming fluorides? :p
<rqou>
rely on just a respirator
<whitequark>
uhm no
<whitequark>
not with HF
<azonenberg_work>
they do actually make HF respirators
<whitequark>
and I don't rely on just a respirator
<azonenberg_work>
But i'm not sure i'd want my skin being exposed to that high a vapor concentration :p
<whitequark>
I use a fume*extractor*
<whitequark>
to remove fumes from reaction area directly
<azonenberg_work>
And then the respirator for whatever it misses?
<whitequark>
just in case
<whitequark>
like maybe it breaks or w/e
<whitequark>
not the extractor
<whitequark>
the flask or something
<azonenberg_work>
Yeah makes sense
<azonenberg_work>
in my case i typically work with very small volumes of chemicals
<azonenberg_work>
and the odor threshold is lower than the IDLH concentration
<azonenberg_work>
and usually, lower than the PEL
<whitequark>
... yes, PEL is where it's at
<azonenberg_work>
So basically if it breaks, or i smell anything, i just would evacuate the area
<whitequark>
I dont want to breathe anything at IDLH
<azonenberg_work>
Lol me neither :p
<azonenberg_work>
Odor threshold for all of my common acids and solvents is < PEL
<azonenberg_work>
not sure about HF, would have to double check
<azonenberg_work>
But i usually use a couple drops of 3% at a time
<rqou>
you obviously don't do enough microfab or organic synthesis
<azonenberg_work>
so i cant imagine there's much vapor coming out
<whitequark>
dilute HF is pretty mild
<azonenberg_work>
Quote of the day :p
<rqou>
so whitequark, are you brave enough to try the "CaF2+sulfuric in a lead pipe" reaction?
<azonenberg_work>
"HF" and "mild" in the same sentence
<whitequark>
rqou: what is the purpose of the exercise
<rqou>
produces HF
<whitequark>
I can just go and buy a canister of HF from rushim
<rqou>
oh right, RU :P
<whitequark>
5.5L for $31
<rqou>
damn
<whitequark>
that's uh...
<rqou>
brb moving to RU to boostrap homecmos :P
<whitequark>
40%
<whitequark>
I think
<whitequark>
right, azeotropic
<rqou>
does RU not have *gasp* terrorists? :P
<whitequark>
no one cares about chemical sale control except for if you're making drugs
<whitequark>
not even substances under CWC
<whitequark>
really, the problem here is what I'm going to do with 5L of 40% HF
<whitequark>
neutralize most of it and dump in the nearest river?
<rqou>
so why aren't there meth labs popping up everywhere?
<rqou>
this is ostensibly one of the "major" concerns in the US
<azonenberg_work>
Because some precursors are stupidly restricted
<whitequark>
no
<azonenberg_work>
like what was it, h2so4?
<azonenberg_work>
i forget what you had trouble getting b/c drugs
<whitequark>
last time I was at rushim someone bought a 70L barrel of methylamine
<whitequark>
without showing ID
<rqou>
what
<whitequark>
they just put it on a pickup truck or something
<whitequark>
but yes, h2so4, hcl, and a few others in the same vein are "scheduled"
<rqou>
huh
<rqou>
those are pretty easy to obtain here in the US
<whitequark>
in practice this means that they'll still sell them to me but I need to pay extra and tell them my name on ID
<azonenberg_work>
lol
<whitequark>
note the phrasing
<whitequark>
oh also there's a company that will downright sell you the one step precursor to amphetamine (phenyl-2-nitropropene) and a few others
<whitequark>
the trick is that under the law you can't sell them in more than ~10% concentration
<whitequark>
so they sell 10% nitropropene
<rqou>
so why doesn't this end up being a problem?
<whitequark>
completely officially
<whitequark>
pay taxes etc
<azonenberg_work>
whitequark: Can you buy methylphosphonyl difluoride in .ru?
<whitequark>
azonenberg_work: what's that
<whitequark>
ah, sarin precursor
<whitequark>
unlikely, it's not useful in synthesis
* azonenberg_work
suspects THAT would raise a few eyebrows
<whitequark>
what I can buy is thionyl chloride
<azonenberg_work>
especially if you bouhgt a big drum of 2-propanol on the same order
<rqou>
is thionyl chloride restricted?
<whitequark>
not really afaict
<rqou>
i thought it's used in batteries?
<whitequark>
it's a CWC substance
<whitequark>
in batteries? doubt it
<whitequark>
it's a very powerful chlorinating agent
<whitequark>
oh wait yeah there's a type of batteries
<whitequark>
rqou: regarding meth labs
<whitequark>
see, in the US, DEA puts pressure on illegal drug manufacturers, so cost and negative externalities skyrocket and quality plummets
<whitequark>
in RU, ruDEA doesn't really care all that much so long as the vendors aren't too brazen, so people generally do it well and well hidden
<whitequark>
you don't have makeshift meth labs poisoning people because there aren't any makeshift meth labs nor any demand for them
<whitequark>
you have drug labs that literally compete with each other on the purity of their product complete with LC-MS traces
<rqou>
O_o
<rqou>
wow
<awygle>
Poisoning people *and* blowing up elementary schools
<rqou>
so why aren't there *gasp* terrorists?
<whitequark>
well, LC-MS traces are not common but quantitative analysis results are
<awygle>
(ask what happened to my elementary school sometime)
<whitequark>
dunno? a) maybe no one actually wants to blow up shit b) maybe terrorism goes under FSB and not ruDEA and FSB is actually interested in tracking and eliminating it
<whitequark>
did you hear one story about ruDEA
* azonenberg_work
says B
<azonenberg_work>
From what i've read about russian counterterrorism, they take a very different approach
<whitequark>
two officers of it were once found dead in a sauna in a ruDEA building. cause of death: heroin overdose
<rqou>
wtf
<rqou>
does ruDEA actually do anything?
<whitequark>
yes
<azonenberg_work>
US counterterrorism: surround the hostage situation, contain it, try to convince them to surrender
<whitequark>
so the organizations name sounds like "govtnarcocontrol"
<whitequark>
but we call it "govtnarcocartel"
<azonenberg_work>
RU: eliminate the threat, leave no survivors, and if you kill a few civilians on the way? so be it
<rqou>
ah, i see
<whitequark>
oh yeah is everything here aware of the moscow theatre hostage crisis?
<rqou>
yeah
<azonenberg_work>
Yes, that's what i was refernceing
<azonenberg_work>
(among other things)
<rqou>
did anybody ever identify what it was?
<azonenberg_work>
the drug?
<rqou>
yeah
<azonenberg_work>
it was a fentanyl derivative iirc
<whitequark>
likely, carfentanil or lorfentanyl
<whitequark>
lorfentanyl has a ng/kg LD50
<azonenberg_work>
but not sure if the exact composition was ever figured out
<rqou>
so is this ruDEA behavior part of the reason RU has an AIDS crisis?
<rqou>
in addition to "the gayz are evil"
<whitequark>
no
<whitequark>
RU has an AIDS crisis for the same reason US has an AIDS crisis
<whitequark>
(it has, if you slice through the right demographics)
<whitequark>
there's shit all to do, no hope, no awareness of PrEP and so on, and no one still strong enough to fight that
<whitequark>
because people who can move to regions where something happens
<whitequark>
i.e. from small cities in urals or siberia to moscow or spb or just larger regional centers
<whitequark>
it's not a drug problem or gay problem
<whitequark>
well, those aren't the root causes, anyway
<rqou>
right, makes sense
<rqou>
english reporting likes to focus on the "gayz are evil" narrative
<whitequark>
see also: tuberculosis so bad WHO had to invent a whole new category, XDR
<whitequark>
basically a death sentence
<whitequark>
that's more of a prison problem though
<rqou>
so when do we get RU-YoureOnYourOwn-TB? :P
<whitequark>
that's XDR
<whitequark>
it's not treatable
<whitequark>
like... not treatable, period. nowhere in the world.
<whitequark>
much less in RU
enriq has joined ##openfpga
enriq has quit [Client Quit]
m_t has quit [Quit: Leaving]
eric_j has quit [Read error: Connection reset by peer]
eric_j has joined ##openfpga
ZipCPU|Laptop has quit [Ping timeout: 248 seconds]