<rqou> cseed?
<rqou> oh wait, that's a fork
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<awygle> These chips are identical.
<awygle> What the hell.
<azonenberg> awygle: hardware issue?
<azonenberg> Break out the sillyscope
<rqou> long shot: did somebody undervolt Vpp while programming?
<rqou> (i bricked a usb-serial converter that way before)
<awygle> azonenberg: too consistent, all the new chips don't work but the old ones do
<azonenberg> awygle: die respin introducing a bug?
<azonenberg> PCB respi nintroducing bug?
<awygle> I am looking at scope traces now...
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<azonenberg> Look at the date codes on the chips, any pattern there?
<azonenberg> is there a H/W version register or stepping number you can query?
<awygle> Would have to be die respin. These are allegedly the same lot...
<azonenberg> Compare chip top marking codes
<azonenberg> and any descriptor registers you can read
<azonenberg> jtag idcode, i2c/spi id registers, etc
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<pie_> <rqou> and you aren't a shitposting cosplaying alchemist girl
<pie_> I THINK I KNOW THIS ONE
<pie_> azonenberg, mmm scuits
<rqou> pie_ go study :P :P
<cr1901_modern> Everybody knows that one
* qu1j0t3 doesn't but that's ok
* qu1j0t3 probably read it but forgot it
<awygle> How old is the Intel hex format I wonder
<qu1j0t3> 70s i believe
<qu1j0t3> do you want a year?
<pie_> i mean i guess this could be a good thing but i doubt its a good thing
<rqou> eh, not any more insane than usual
<pie_> one does not simply sack a bunch of their diplomats....do they?
<pie_> unless theyre going to replace them with better people *eye-rolling optimism(
<Bike> just keepin everybody on their toes, no doubt
<azonenberg> pie_: the goal is less diplomacy happening
<azonenberg> less people accomplishes that
<pie_> :|
<pie_> why i that good for anyone
<pie_> *is
<Bike> are you just now seeing 2017
<pie_> Bike, im still avoiding it
<Bike> that's fair.
<rqou> i thought hungary would also be experiencing 2017? :P
<pie_> idk, i nly really keep up with politics as much as i run across on the internet
<Bike> my paycheck comes from a dude who didn't know what the department did and thought it should be shut down. 2017 is very 2017
<rqou> although problems with trump get a lot more attention than problems with migrants
<pie_> and a lot of the trump related stuff ive just not been looking at
<pie_> oh right that stuff
<pie_> well, rule of law still seems to stand here *glances around*
<pie_> perception being key
<pie_> good god america wtf
<Bike> most of the secret police options are actually not liked by trumpists, with the exception of ICE, so they have to do nazi rallies instead, you know?
<pie_> im already ashamed of calling myself american
<rqou> aren't you still in hungary?
<pie_> i am
<pie_> so i just dont bring it up lol
<rqou> (not that that's much better)
<pie_> its not bad?...
<pie_> i mean the US is still in a stronger economic position regardless
<Bike> rate the situation in millipolands
<pie_> all things considered hungary is probably relatively sane?
<rqou> except the migrant crisis?
<pie_> the thing is ive got no insight into these things :P
<qu1j0t3> rqou: Do you mean refugees ?
<rqou> yes
<pie_> also i suppose the propaganda machine doesnt really grind here since budapest is what counts the most
<pie_> so i guess im missing most of the action, hence i cant really comment
<pie_> actually
<pie_> i guess the reason things are sane here is this is a rather sleepy city and i dont get out a lot
<pie_> its easy for the world to seem sane when you dont talk to people
<qu1j0t3> i lived very far from the city for many years. It was idyllic. No 'net either.
<pie_> re: why is less diplomacy good for anyone?
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<pie_> of all things idk why im getting hung up on the "foreign policy department" getting gutted
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<Bike> well, imagine if every complex problem was just a farce put into place by greedy bureaucrats eager to bleed you, and that actually a bit of effort would solve all problems worth solving
<pie_> ok time to not read anything about politics for two months
<pie_> good god next election in 2020?
<pie_> why is it so far
<Bike> there's midterms, if you like
<pie_> iwonder what the person that inherits this steaming pile of shit will be able to do
<pie_> assuming noncontinuity of this administration
<pie_> which im not sure is a fair assumption
<awygle> Okay so these chips have shadow registers apparently so when I was comparing I wasn't getting the right data. Poking one of them makes some, but not all, of the new chips work.
<rqou> is the identity of this chip a secret?
<awygle> Good enough for today, will debug tomorrow
<awygle> I am working on UFS devices
<awygle> For $DAYJOB
<azonenberg> awygle: lol great
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<jn__> https://twitter.com/oe1cxw/status/935318202942349312 <-- oh wow. Mathias L (the original ice40 reverse engineer) is giving a talk at 34c3 on how he reverse engineered xilinx 7-series, and this is independent of clifford's effort. fun.
<lain> hee
<awygle> #drama
<awygle> As a relative noob I've never heard of Matthias L
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<pointfree> Whose talk is scheduled first? Clifford's or Mathias'? :)
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<jn__> they're not yet scheduled
<jn__> you can help make sure they're not scheduled to the same time slot by using halfnarp
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<azonenberg> Welp, one more reason to replace vivado et al
<azonenberg> anybody wanna try reproducing? :p
<cr1901_modern> I've had said in the past, only _somewhat_ jokingly, that the motivation for FOSS FPGA is that vendor tools suck. Badly.
<azonenberg> cr1901_modern: lol
<cr1901_modern> (Okay so there are sadly things that ISE/Vivado can do that icestorm can't. Mostly related to timing analysis for me.)
<azonenberg> I'm working on a good timing engine for greenpak so we'll see what comes of that
<azonenberg> I want to try and do cross-clock analysis and good combinatorial stuff etc
<azonenberg> timing driven P&R
<azonenberg> and so on
<cr1901_modern> cross-clock analysis is really only predictable if the clocks have a known phase relationship, right?
<cr1901_modern> (read: you can calculate the minimum time difference between two edges of separate clocks)
<azonenberg> Correct
<azonenberg> But sometimes you can do that
<cr1901_modern> right, DCM output for example
<azonenberg> greenpak does a lot of stuff with gated clocks too
<cr1901_modern> ahh
<azonenberg> so i want to support those well
<azonenberg> none of the stuff has CE inputs
<azonenberg> you're expected to use lut logic to gate the clock and/or mux the inputs
<azonenberg> So i want to be able to properly analyze the extra logic delay in the clock path
<cr1901_modern> (And of course, icetime only supports a single constraint even if you're not concerned w/ cross-clock analysis)
<cr1901_modern> I've actually never tried, will Xilinx attempt to analyze a multi-reg at a CDC if you forget the false-path constraint?
<azonenberg> iirc it will get very confused then fail because the phase can go to zero - iff the clocks are derived from the same source
<azonenberg> If they're different sources i think it just forgets it even happened?
<cr1901_modern> Hmmm, interesting.
<azonenberg> Also look at that
<azonenberg> somebody replied to my post already confirming the bug
<cr1901_modern> lol
<cr1901_modern> For the record, I have omitted the multi-reg for CDC from src clock to DCM output, and Xilinx handles that fine
<cr1901_modern> (i.e. no timing failures)
<cr1901_modern> in fact that's what compelled me to look up whether Xilinx could handle cross-clock analysis... I didn't want to do a multi-bit CDC :P
* cr1901_modern is lazy
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<azonenberg> cr1901_modern: grrr
<azonenberg> so apparently the mod is saying he cant reproduce my bug
<azonenberg> Anybody have an ubuntu LTS system to test on (or another officially supported OS)?
<azonenberg> Or do i have to go spin up a VM and download vivado just to make the guys happy :p
<azonenberg> clifford really has to finish REing 7 series asap so we can get a usable par going :p
<cr1901_modern> azonenberg: I do have xubuntu lts, but I'm not installing vivado at 2:30am in the morning
<cr1901_modern> Considering I have _no_ dev boards that can use it
<azonenberg> lol
<azonenberg> well i just need a sim tested
<azonenberg> To confirm a bug
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<rqou> wait, only 16.04 is supported?
<rqou> i was going to test for you, but my install is too _old_ :P
<rqou> i apparently don't have the latest vivado installed anyways
<azonenberg> Yes only ubuntu 16.04
<azonenberg> or redhat
<rqou> yeah my install for vivado is still 14.04 and not the latest vivado
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<pie__> <jn__> you can help make sure they're not scheduled to the same time slot by using halfnarp
<pie__> cool
<pie__> itd about time someone did somethng like this
<jn__> halfnarp is not new
<jn__> (i mean: it existed last year. i don't know *how* old it actually is)
<pie__> ive never heard of other conferences having something like this, then again idk how i would have so might just be my sampling bias :P
<qu1j0t3> i'm getting flashbacks to using a student registration system to enrol mrsfb in uni courses a while back, omg. What awful software...
<awygle> pie__: I missed that you posted Akin's Laws the other day. My dad had those on the wall when I was growing up but I haven't thought about them in years. Holy shit they are so accurate now
<qu1j0t3> awygle: I'm reading Bob Pease at the moment. These laws are new to me, but remind me a lot of Pease :D
<qu1j0t3> awygle: I first heard #41 working with old-timers in graphic repro
<qu1j0t3> gj pie__ thanks
<awygle> Some of them cross industries better than others. "no new launch vehicles" is quite unlikely to come up in graphics
<awygle> "multiply estimates by pi" however is just good advice
<qu1j0t3> i'm able to filter appropriately :)
<qu1j0t3> a lot of these have arisen in CS too
<qu1j0t3> or rather, sweng
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<awygle> "stepping" refers specifically to die *revision*, not like, a process shrink or a totally new die, right?
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<azonenberg> awygle: correct
<azonenberg> well, depending on the chip vendor a small shrink of an unchanged mask set might be a new stepping
<azonenberg> i remember hearing microchip did that with one pic and had problems with the ADC as a result?
<azonenberg> iirc crosstalk between a GPIO and the ADC input
<qu1j0t3> it would be deadly for mixed signal wouldn't it? all the passives would change
<azonenberg> qu1j0t3: i dont know how much they shrunk
<azonenberg> i just remember hearing the story like thirdhand
<azonenberg> maybe they redid the IP block and not the routing around it?
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<qu1j0t3> sounds reasonable
<qu1j0t3> looks like i'm going to switch to the Freedom Kinesis platform for my own stuff... tired of fighting arduino knockoffs :)
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<azonenberg> So this is interesting
<awygle> azonenberg:.... Yes?
<awygle> Oh I see, you finished the thought in ##fpga
<azonenberg> yeah i meant to post in that chan
<awygle> Riscv WD news is cool
<awygle> 1bn RISC-V cores
* qu1j0t3 should i lurk in ##fpga
<awygle> It's higher volume than here and there's a higher student/spam quotient
<qu1j0t3> ok i'll rely on people to post GOOD CONTENT in here then
<qu1j0t3> sfsg
<digshadow> awygle: this chan does have politics though it seems
<pie__> jn__, i only now realized i posted it in the wrong channel
<pie__> nvm right channel
<pie__> i post THE BEST content in here. #MOGA
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<rqou> whee, just wasted a bunch of time messing around with networkmanager/wpa_supplicant _AGAIN_
<rqou> i'm never upgrading these packages anymore as long as i can
<rqou> felix_: somebody please go RE the wl.ko driver too kthx
<rqou> :P
<qu1j0t3> rqou: wow, yeah, i've spent far too many hours on that
<rqou> somehow they keep perturbing it and breaking it/fixing it again and again
<rqou> does anybody ever even test these? maybe only on ath9k?
<jn__> wl.ko? which platform is this?
<jn__> (hardware platform)
<qu1j0t3> ..i think that might have been the platform i was using..
<rqou> wl.ko is broadcom's shitty driver
<rqou> for e.g. macbooks
<qu1j0t3> (ath9k that is)
<rqou> IME ath5k and ath9k are the only "actually working" wifi chipsets
<qu1j0t3> (definitely an atheros of some kind)
<rqou> (on linux)
<qu1j0t3> (and linux)
<rqou> ath10k is kinda shitty because qualcomm got their hands on it
<awygle> Yeah ath9k or bust
<rqou> but it has no AC
<rqou> you should help RE ath10k
<awygle> Didn't Qualcomm open ath10k?
<rqou> no
<awygle> I stopped paying attention right as that came out
<rqou> there's a firmware blob
<rqou> it's lz-compressed xtensa code
<awygle> Wow, fun
<awygle> I thought they had like a hal or something
<rqou> me and felix_ and one of felix_'s friends are supposedly working on this
<rqou> but ENOTIME
<pie__> rqou, no unit tests im guessing
<pie__> yeah ok ok just "no tests" is enough i gues
<pie__> "-You look at a "whitepaper" and realize that if this were a research paper in any other field of study, the author would have been crucified by their peers"
<pie__> *cough-hack-wheeze*
<awygle> I'm not sure how I ended up with so much infosec on my Twitter but it's depressing and I was enjoying my ignorance tyvm
<pie__> awygle, wait is that like me and politics
<pie__> >>> profound implications
<openfpga-github> [openfpga] rqou pushed 2 new commits to master: https://git.io/vbU9F
<openfpga-github> openfpga/master ed79723 Robert Ou: xc2bit: Remove manual Clone traits...
<openfpga-github> openfpga/master c783e2b Robert Ou: xc2bit: Autoderive more traits...
<qu1j0t3> pie__: profound?
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<jn__> pie__: File "<stdin>", line 1
<jn__> profound implications
<jn__> SyntaxError: invalid syntax
<jn__> ^
<jn__> :P
<jn__> (and sorry for the spam, i liked the joke)
<pie__> ;D
<pie__> wait
<pie__> so any greentext deep enough is just a python EDSL!?
<pie__> >>> profound implications!
<awygle> My showerthought on this is that we're in the industrial revolution of computing, where we do great things by externalizing profound costs, and eventually we'll have the green movement where we try to fix a bunch of this shit
<qu1j0t3> awygle: arguably open source was one of those reactions
<qu1j0t3> awygle: but we'll all be 50 feet underwater first...
<azonenberg> awygle: you mean bitcoin? :p
* qu1j0t3 faints
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