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<qu1j0t3> pcb field solver? this sounds interesting.
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<pie_> pcb field solver? i feel like im working on getting a phd just to write an acceptable gui...
<cr1901_modern> I wish "placing objects in a grid" wasn't the topic of phd theses
<rqou> eh, just make a command-line field solver like all "traditional" EDA tools :P
<rqou> make sure it's driven by a tcl script
<rqou> and make it accept a silly text input format based on s-expressions
<rqou> or maybe be a bit more "modern" and accept XML :P
<rqou> for bonus points, make sure the graphical output can be viewed by rendering it to ascii art
<rqou> :P :P
<rqou> azonenberg am i doing it right?
<pie_> stop
<pie_> pleease
<pie_> alternatively, hurt me more
<rqou> l-lewd :P
<azonenberg> eeeew
<azonenberg> no, i want something sane
<azonenberg> Have it import say kicad layout files
<UmbralRaptor> rqou: Should cover the entire BMP, notably the box drawing characters.
<qu1j0t3> people. people.
<rqou> o/ UmbralRaptor
<azonenberg> and export to some standard interchange format
<rqou> nice to see you here too
<pie_> azonenberg, thats the joke
<UmbralRaptor> Been lurking, but egg is missing, so… ¯\_(ツ)_/¯
<rqou> azonenberg: standard interchange format, like a .blend file? :P :P
<pie_> actually strangely enough even im saying s expressions arent thaaat bad, though there are some things in scheme that are are uncomfortable imo
<rqou> so kicad legitimately uses s-expressions in data files
<qu1j0t3> go on
<rqou> but you don't have to write them by hand
<rqou> probably better/more consistent than the old scanf-based parser
<rqou> azonenberg: .dxf is a standard interchange format, is it not? :P :P :P
<pie_> on the other hand, prefix notation makes complicated math expressions fucking unreadable
<pie_> though i should shut up since ive got like a couple days of scheme under my belt at most :P
<pie_> i havent rewritten the universe yet
<rqou> i did :P
<pie_> yeah well some of us are a little slow to the party ok? :PP
<rqou> we wrote a scheme interpreter in our intro cs course (which used to also be taught in scheme but was ported to python (poke poke awygle for a possible rant?))
<pie_> poke qu1j0t3 for definite rant
<qu1j0t3> oh hell naw i won't rant in here
<pie_> lol
<rqou> does the rant involve SICP?
<qu1j0t3> i am out of rants
<qu1j0t3> 4 week backorder
<pie_> its great when you rewrite a bunch of code to conform to an idea you have because you cant tell beforehand if it will work. the whole time hoping that it will work. pls work
<qu1j0t3> i can't say much about sicp since i haven't even finished CH.2
<rqou> use our Python port of SICP instead? :P :P
* rqou is goading awygle into a rant
* qu1j0t3 frowns
* pie_ attempts to convince himself to leave for the day
* awygle is actually busy for once
<rqou> awygle: so i forgot, did you actually take the classic bh-taught 61a or the new python 61a?
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<awygle> rqou: the OG. and i loved SICP so any rant would actually be quite positive (and possibly anti-python)
<rqou> yeah i was trying to goad you into an anti-python rant :P
<rqou> oh wait azonenberg hates python too iirc? can we get an anti-python rant?
<rqou> :P
* rqou imports antigravity
* pie_ imports mail order brides
<cr1901_modern> SICP was/is a tough read for me.
<rqou> but pie_ you're in eastern europe
<rqou> that's where we _get_ mail order brides from :P
<pie_> and where do you think we get ours? :D
<rqou> even eastern-er europe :P :P
<awygle> cr1901_modern: any particular reason?
<rqou> wasn't taught by the legendary brian harvey :P
<cr1901_modern> Just hard for me to think in the FP mindset
<cr1901_modern> It's not a bad book. It's just difficult
<awygle> huh, if asked i would have guessed you were a Haskeller for some reason
<cr1901_modern> Hahahahahahahaha no!!
<cr1901_modern> I can't even finish structuring an OCaml program, let alone a Haskell one
<mtp> i can structure a haskell program!
<mtp> i just can't make it _do anything_
<mtp> the pure subset fits in my brain and the effectual subset does not
<cr1901_modern> awygle: And, tbh every time I use Lisp I always end up needing something resembling a sum type
<rqou> first you need to make an analogy with a sandwich/burrito/whatever-people-use
<cr1901_modern> and SICP didn't really help me figure out what to do there
<Bike> like a proper union?
<cr1901_modern> Idk what you mean by proper, but yea sure union work
<Bike> dunno if i've ever wanted one other than maybe... how strange
<pie_> sicp helped me stop being so afraid of recursion
<pie_> types are a different matter for now
<rqou> yup, the curriculum here really likes recursion
<cr1901_modern> Bike: Tried writing an assembler in lisp. Kinda need to dispatch on the resulting AST from the first pass
<Bike> also, there's something kind of weird about seeing someone say they can't use haskell and then talk about sum types
<Bike> oh. i'd just use objects or structs or whatever
<Bike> which i don't think r4rs has
<Bike> (sicp was r4rs, right?)
<pie_> r5 maybe
<qu1j0t3> cr1901_modern | and SICP didn't really help me figure out what to do there || right, that's a different world.
<cr1901_modern> qu1j0t3: The point I'm trying to make is that while CL and Scheme _add_ data structures to help me do what I what, I get
<cr1901_modern> the vibe they are decidely un-lispy
<Bike> i guess those are sum types, huh. i don't know shit about anything
<qu1j0t3> yep.
<Bike> "lispiness" is silly, it's just a computer program, not a painting
<qu1j0t3> cr1901_modern: it's not really a coincidence. these things developed not only in different intellectual hemispheres, but largely on different continents too.. which don't always freely share ideas
<qu1j0t3> cr1901_modern: and now they fight like cats and dogs, so i just do what i think is best *rhsug*
<cr1901_modern> Well then how is the SICP world supposed to operate on an AST? How do they distinguish different nodes from each other?
<cr1901_modern> Sure I guess I could use an list w/ an id obtained through cdar
<qu1j0t3> pie_ | sicp helped me stop being so afraid of recursion || Hooray! That's a big reason why i recommended it.
<awygle> cr1901_modern: tag them with symbols, iirc
<qu1j0t3> awygle: for good ole runtime checking.
<Bike> i don't think the scheme sicp is written with is great for most software. in later scheme revisions they added tons more shit, after all
<awygle> qu1j0t3: well, R5RS is almost entirely untyped, so unless you want to write a macro....
<qu1j0t3> awygle: Oh, i know.
<cr1901_modern> I don't mind using, for instance, a hash table provided by scheme b/c f*** you I'm not implementing my own
<awygle> CL is a much more pragmatic lisp than scheme is
<cr1901_modern> ENOINTEREST
<pie_> i was actually suprised when i found out clojure is a lisp
<qu1j0t3> awygle: Further away from my interests, then.
<pie_> i had no idea
<awygle> people keep telling me to learn clojure
<cr1901_modern> awygle: What do you mean by "symbols"?
<awygle> not a fan
<qu1j0t3> pie_: "Sort of"
<rqou> iirc part of the reason our intro course got ported to python is because nobody used scheme "for real" but a lot of people use python "for real"
<pie_> (i mean id never seen clojure, just heard of it)
<cr1901_modern> just (define my_sym 0)?
<qu1j0t3> awygle: I have no use for it either
<rqou> clojure as in the jvm thing? eww
<Bike> (list 'foo-ast ...data goes here...)
<Bike> i assume
<rqou> i've not had a good experience with that
<cr1901_modern> oh right, the quote bullshit
<rqou> cr1901_modern probably knows what project decided to use clojure "cleverly"
<awygle> lol
<pie_> rqou, hm? :P
<cr1901_modern> I don't remember
<rqou> J-core's microcode processor
<cr1901_modern> Oh, that
<Bike> wow, what?
<pie_> rqou, whats that
<cr1901_modern> it parses an excel datasheet
<pie_> btw chicken scheme release 5 sometime in the near future
<rqou> let's just say it overall turns a .ods into a .vhd file
<cr1901_modern> to spit out VHDL or something
<Bike> oh dear.
<pie_> for whatever appropriate value of near
<pie_> um
<pie_> wat
<awygle> iirc my favorite was racket, last time i did any scheme (which was like 5 years ago and i embedded it as a game scripting language)
<Bike> you don't mean, like, in the running processor?
<cr1901_modern> Bike: "and then talk about sum types" I mean, fair I guess? I only know what a sum type is because someone in a FP Slack explained it to me
<qu1j0t3> except we use them all the time
* qu1j0t3 shrug
<pie_> qu1j0t3, we breathe all the time but understanding respiration isnt necessarily simple :P
<Bike> but don't know what they are.
<qu1j0t3> pie_: jesus
<qu1j0t3> pie_: stop
<qu1j0t3> pie_: C even has product-type-kind-of-things.
<cr1901_modern> I've never unconsciously implemented a monad, fwiw
<pie_> honestly i have no idea what a sum type is, unless something = a | b
<cr1901_modern> some ppl seem to think it's a common thing to implement yourself
<pie_> qu1j0t3, considering i hang out in ##dependent im pretty fuckin clueless
<Bike> i only know any type stuff because i used to hang out with people who were like "check it out, just implemented the coyoneda monad" so i sympathize
<pie_> in which case i can kind of guess
<qu1j0t3> pie_: even C has sum-type-kind-of-things. it's really stuff we do every day.
<qu1j0t3> pie_: you can't tell me it's a complicated concept.
<Bike> respiration? it kind of is. i mean, it's not that hard to understand, but you still don't really know the details of TLC versus TV, probably
<cr1901_modern> it's called a struct
<pie_> ok im getting sidetracked again xD
<qu1j0t3> pie_: except that now we know there are principled ways of handling them.
<Bike> plus there are plethysmographs, by all accoutns an awesome word
<pie_> Bike, heck that does sound awesome
<pie_> oh i thought that was a type theory thing lol
<Bike> no i decided i would talk about something completely unrelated
<qu1j0t3> pie_: anyway if you want to study mandibles, start with Wadler 1991
<cr1901_modern> pie_: A monad is actually the foldable flap of skin behind a cat's ear
<cr1901_modern> (fun fact: That actually has a name. It's called Henry's Pocket. And nobody knows what it does)
<Bike> type shite has like, "hylomorphism", the only entry in Design Patterns In Haskell invented by aristotle
<Bike> wow, that thing has a name. i wonder how long i'll remember that.
<qu1j0t3> um
<qu1j0t3> many words we use have greek and latin roots. words are not scary.
<Bike> who's scared by aristotle?
<qu1j0t3> ever seen a catalytic converter.
<qu1j0t3> a pantograph
<cr1901_modern> what are you getting at?
<qu1j0t3> why does it suddenly become scary when it's technically relevant to our profession.
<Bike> i'm not scared of hylomorphisms. i could beat up a hylomorphism.
<cr1901_modern> B/c it takes hours to explain before someone actually gets it
<qu1j0t3> my dad could beat up a daddy catamorphism
<qu1j0t3> so there
<cr1901_modern> qu1j0t3: I barely understand what a monad is. It took me 4+ hours talking one-on-one with the author of "FP for Rubyists" before I got it
<Bike> hylomorphisms are actually easy, wikipedia gives the example of factorial, everyone's favorite function that's useless until you extend it to reals anyway
<qu1j0t3> cr1901_modern: read Wadler 1991
<cr1901_modern> qu1j0t3: And even then I only understand that it in terms of fmap() and bind()
<qu1j0t3> Bike: it's all tractable once the fear and loathing is brushed away
<cr1901_modern> Is there a use for linear logic?
<Bike> monads are pretty easy too.
<cr1901_modern> that one?
<Bike> i still don't know what linear logic is though. people seem excited about it though.
<cr1901_modern> Thing that Rust uses
<Bike> it seems like people sometimes get really excited about these things and do all this abstract stuff that seems really wacky and then a few years later someone dumbs it down and we're all eating burritos without knowing any math
<awygle> does rust have higher kinded types yet? people seem to think that would be a good thing to have
* cr1901_modern waits to be corrected
<cr1901_modern> awygle: No and it probably won't
<cr1901_modern> Oh yea, that's another thing. Once I learned how a functor works, I was like "cool, can I express functor trait in Rust?"
<cr1901_modern> and the answer is "not without HKTs. It's not possible to write the type sig without them"
<cr1901_modern> Or something like that
<pie_> holy shit! my code works! this is largely but not entirely unexpected. send me cookies. ive reached peak performance. im stopping while on the top. thats it for today.
* pie_ stares at the huge menacing kludge with no idea how to fix it
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<azonenberg> wootwoot
<azonenberg> Plugfest somewhat successful
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<azonenberg> My PHY is able to auto-negotiate 100baseTX full duplex with my laptop
<azonenberg> Bring up the link
<azonenberg> and send hard-coded UDP packets to the PC
<azonenberg> The RX side is unreliable and isnt syncing well
<azonenberg> but works in loopback
* whitequark reads backlog
* whitequark stares at rqou
<awygle> 6
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<awygle> azonenberg: nice
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<azonenberg> It even works through my switch, i can wireshark from my desktop
<azonenberg> But the RX needs debugging
<azonenberg> i can RX my test packet in loopback
<azonenberg> so either my thresholds are too aggressive, or i'm too pedantic with timing, or something else
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<rqou> whitequark: what?
<rqou> about lab safety?
<whitequark> yes
<whitequark> and explosives
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<rqou> i actually haven't synthesized any explosives and don't actually intend to
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<rqou> azonenberg: lol RX is always harder than TX
<azonenberg> rqou: The two things i am not doing that a real PHY would, and which i *know* will hurt my max range
<azonenberg> are equalization and adaptive thresholds for baseline wander correctoin
<azonenberg> correction*
<azonenberg> My TX waveforms are, to the extent of my measurement accuracy, fully 802.3 compliant
<rqou> after you finish, you should rent an ixia/spirent test set :P
<azonenberg> ?
<rqou> to actually fully verify compliance
<azonenberg> I know for a fact that my RX is not compliant, and it wont be
<azonenberg> but IDGAF
<azonenberg> i just want to get it to work
<azonenberg> TX side, OTOH, i can already qualify everything is compliant but the jitter
<azonenberg> and i could measure jitter if i had a faster scope
<rqou> now try it with the max cable length :P
<rqou> (iirc my father's company failed this once by using a realtek phy)
<rqou> but only on the management interface, so everyone went ¯\_(ツ)_/¯ and ignored it
<rqou> eventually realtek phys got banned due to too many errata :P
<azonenberg> lol
<azonenberg> The IEEE spec is, afaik, for performance at the TX magnetics
<azonenberg> Since cables degrade everybody's signal the same
<rqou> ah, so maybe it was even still spec compliant
<rqou> :P
<azonenberg> Its more likely that the RX failed at a max-length cable
<rqou> probably
<azonenberg> Because the spec says the min amplitude you're allowed to recover, max jitter you must accept, etc
<azonenberg> And i know for a fact my phy will fall flat on its face with that
<azonenberg> it's meant for short runs
<azonenberg> And, honestly, just for lulz :p
<azonenberg> I just want to make it work with a usefully long (1-2 meter) cable and not a loopback adapter
<azonenberg> My guess is, the failure isnt due to signal degradation in the cable
<azonenberg> its due to the other PHY not being on my clock
<azonenberg> triggering some bug somewhere in my RX datapath that is hidden by the exact phase sync i have now
<rqou> CDR is hard
<azonenberg> I have what SHOULD be a good CDR block
<azonenberg> but its never been tested with data that wasnt generated on my clock
<azonenberg> with a fixed phase offset from the cable :p
<azonenberg> aaanyway i should sleep
<azonenberg> i'll debug the CDR more tomorrow
<azonenberg> Basically i oversample the incoming signal 4x (at 500 MHz) with an ISERDES, then i process 4 bits at a time and output a variable-rate bit stream
<azonenberg> The incoming signal is nominally one symbol per 125 MHz cycle but there may be jitter or slight frequency mismatches
<azonenberg> So I output two bits and a "number valid" count
<azonenberg> and thus can generate 0, 1, or 2 data bits per 125 MHz cycle
<rqou> no PLL?
<azonenberg> No, I resync every edge like a UART
<rqou> er, most trivial uarts don't resync
<rqou> only on start bits
<azonenberg> The hope is that, barring pathological "killer packet" cases where the packet data post-4b5b phase aligns to the LFSR
<azonenberg> I will have a sufficient number of edges per unit time
<azonenberg> that I can remain approximately synced
<azonenberg> anyway I then shove that stream of bits into a shift register 1 or 2 bits at a time, create a stream of 5-bit words (which may not be actually aligned to 4b/5b symbol boundaries)
<azonenberg> unscramble with the LFSR
<azonenberg> then use the "start of frame" 4b5b code to get symbol sync
<azonenberg> then decode the 4b5b
<rqou> don't worry, your killer packets won't be as bad as SDI :P
<azonenberg> feed through an elastic buffer to rate match to the MII clock (up until this point I'm dealing with sparse 5-bit frames at 125 MHz so I can tolerate significant changes in dat rate)
<azonenberg> and spit out the MII interface
<rqou> azonenberg did you know that SDI can generate a stream of 19 contiguous bits with a certain pink color?
<rqou> this is the reason they need special SFPs with altered AGC behavior
<azonenberg> 100baseT can do worse than that
<azonenberg> with a certain weird packet
<rqou> it can?
<azonenberg> basically you send this magic data over and over
<azonenberg> and every second or so, you get lucky
<azonenberg> and your 4b5b code stream exactly matches the scrambler output
<rqou> i thought the ieee bit stuffing specifically prevented this problem
<azonenberg> and the xor gives a long run of 0s or 1s
<azonenberg> there is no bit stuffing
<azonenberg> they 4b5b and *then* scramble
<rqou> wait wait what
<rqou> i thought ethernet was 8b10b?
<azonenberg> Gig over optics is
<azonenberg> 100 over copper is 4b5b and then xored with a LFSR
<rqou> oooh only copper has this problem
<azonenberg> Gig over copper uses a different scrambler without this problem
<azonenberg> 10M over copper uses manchester which is also immune
<rqou> so only 100base-t specifically has this problem?
<azonenberg> Anyway, with 100base-TX a specially crafted stream of 4-bit symbols can produce a stream of 5-bit code groups
<azonenberg> which is equal to, or the complement of, N consecutive bits of the scrambler LFSR
<azonenberg> So if you send this magic data in a tight loop eventually you'll line up with the 11-bit LFSR
<rqou> hmm
<azonenberg> and get a long run of all 0s (no transitions)
<rqou> ok, finally a contender for "worse than SDI's crappy scrambler"
<azonenberg> which can cause either CDR failures
<azonenberg> or, worse yet, DC balance errors
<rqou> hilariously, afaik SDI over copper doesn't have too many issues with their scrambler
<rqou> because coax isn't dc-blocking
<azonenberg> lolol
<azonenberg> If you have baseline wander correction in the HY
<rqou> but then they put the same coding on optics
<azonenberg> PHY*
<azonenberg> you can get away with a lot
<azonenberg> aaaanyway, i'm gonna go to sleep
<azonenberg> and debug this after work tomorrow :p
<rqou> goodnight
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<gruetzkopf> sdi killer-pink is always fun
<gruetzkopf> i've heard of a video equipment manufacturer that ended up with that color as their blanking color..
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<azonenberg> loool
<azonenberg> rqou: any references to the exact failure mode of the scrambler?
<azonenberg> cant find citations on it
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<rqou> azonenberg: the keyword to search for is "sdi pathological pattern"
<rqou> because everything in the "pro AV universe" is dumb in some way
<rqou> actually, anything related to AV at all is dumb in some way (see HDMI, DP)
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<pie_> random keyboard firmware reversin https://geekhack.org/index.php?&topic=72262.msg1796931#msg1796931 (nothing too fancy)
<azonenberg> rqou: whats wrong with displayport? other than VESA closing the spec after they had a good thing going
<rqou> DP is actually "ok"
<rqou> not being open is annoying though
<azonenberg> Older DP versions are open though
<azonenberg> you just can't do 4k with the open version
<azonenberg> i think 1080p60 is fine
<azonenberg> Which is honestly adequate for anything i am likley to homebrew any time soon
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<rqou> but i do want to be able to do 4k and MST and to pwn the DRM
<rqou> i guess each of these can probably be REd
<azonenberg> awygle: Also, did you see clifford's tweet about the 7 series routing block?
<azonenberg> sounds like he's making good progress REing 7 series switch boxes
<awygle> azonenberg: yup, exciting times
<rqou> yeah, time for you guys to get VPR or something working
<rqou> :P
<awygle> Yeah fair
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<awygle> Life got all lifeish for a while
<awygle> At the risk of sounding like rqou, why are the lower levels of protocol stacks always so completely inappropriate for the higher levels?
<awygle> UFS has some issues but what makes it a horrible protocol is UniPro
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<azonenberg> awygle: my biggest complaint is TCP and UDP
<azonenberg> Putting the checksum at the start
<azonenberg> So you cant do inline streaming
<azonenberg> you're forced to add latency by buffering the entire packet, checksumming, then putting the checksum at the start of the packet
<azonenberg> and only THEN can you send it out on the wire
<awygle> Yup, that's real dumb
<azonenberg> 802.3 has it right
<azonenberg> crc at the end
<azonenberg> Workaround: use UDP over IPv4 where the udp checksum is optional
<azonenberg> then add your own optional inner layer CRC at the end of the packet
<azonenberg> IP header checksum is at the start but thats headers only and can be precomputed
<azonenberg> then fixed UDP header, then data, then checksum inside the udp encapsulation
<awygle> At what level do you disable the UDP checksum?
<awygle> Is that a userspace option to socket creation or what?
<azonenberg> That i dont know
<azonenberg> i just know the RFC says its optional
<azonenberg> i've never disabled it except in my own TCP/IP stacks
<awygle> Hm. Might be relevant to my professional interests - I should look into it
<rqou> oh yeah, somehow linux bridging code had problems with this
<shapr> can a crc be incrementally computed?
<awygle> Looks like a simple setsockopt with SO_NO_CHECK
<shapr> that is, could you use the CRC at the front to drop a packet early?
<rqou> there's a "fix checksum" iptables rule that you need to make dhcp/dns work over a bridge with one end being in a container
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<awygle> shapr: you mean predict in advance that it's gonna be wrong? Almost certainly no
<shapr> I was thinking of the DER/BER ASN.1 encodings, where one is easy for the encoder, and one is easy for the decoder
<shapr> azonenberg: for 802.3, you were talking about the FCS?
<azonenberg> Yes
<shapr> yeah, 32 bit crc at the end
<shapr> 'frame check sequence'
<shapr> I just wrote an 802.3 ethernet frame parser in C++ a coupla weeks ago
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<shapr> though I'm having way more fun parsing SIP/SDP in Haskell this week
* azonenberg is writing an 802.3 100base-TX PHY in verilog :p
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<shapr> why 802.3?!
<pie_> shapr, what lib are you using to handle the binary stuff
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<azonenberg> shapr: Because i can
<awygle> Ethernet is a good protocol, generally
<shapr> but ... why not Ethernet II ?
<azonenberg> oh
<azonenberg> This is a PHY, not a MAC
<shapr> ohh
<azonenberg> it doesnt care what the framing is :p
<azonenberg> i'm building a PHY from scratch with an FPGA and some resistors
<azonenberg> No external active components, no PHY chip, no opamps, no ADCs, no DACs
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<shapr> pie_: my team is rewriting my company's half-assed passive TCP/IP stack in C++
<azonenberg> It works in loopback mode, it can bring up a link with my laptop and cisco switch, and i can send a hard-coded UDP packet to my PC in a loop
<pie_> thought you sais haskell
<azonenberg> But i can't read packets sent by another PHY
<shapr> but for Haskell, I'm just using megaparsec to parse SIP/SDP text
<awygle> Always constrain your clocks, kids
<pie_> oh thats text
<azonenberg> Debugging that now, i suspect it's due to the slower rise times of the signal through a long cable causing me to mis-parse
<awygle> Yesterday: "everything works, I have nothing to do"
<awygle> Today: "everything is broken and I have no idea why"
<pie_> awygle, just anotherday eh
<pie_> you might say yesterday was atyical
<pie_> *atypical
<pie_> qu1j0t3 youve made me such a pessimist :P
* qu1j0t3 apologises
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<ZipCPU> azonenberg: Do you know if yosys supports PSOC5?
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<azonenberg> ZipCPU: for synthesis, i'm not sure status is
<azonenberg> not sure what the*
<azonenberg> pointfree and cyrozap have been doing a bunch of RE of the bitstream structure and understand most of it by this point iirc
<azonenberg> but they've mostly been doing some weird Forth-based design entry flow and not verilog
<azonenberg> So i dont know if anyone's ever made a conventional HDL flow for it
<ZipCPU> Thanks! That's the information I was looking for.
<rqou> iirc pointfree wanted to do clever stuff with logic in the routing fabric
* ZipCPU was trying to answer wsm__'s question(s) on #yosys
<rqou> which i don't know enough about nor do i understand how to teach yosys about it
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<Dolu2> Hoy hoy hoy
<rqou> azonenberg: is there a good tl;dr on the psoc fabric? I read our wiki notes and still understand basically nothing
<azonenberg> rqou: ive been poking them to write one for a bit
<azonenberg> i dont fully underdstand their notes :p
<rqou> a glossary would be nice :P
<pointfree> rqou: http://www.psoctools.org/
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<rqou> pointfree: but i'm still not clear, exactly what is PRT, UDB, DSI, HV, HC?
<pointfree> PRT = port (8 gpio pins)
<pointfree> UDB = Universal Digital Block (contains PLD's, datapath, status & control, clocking, reset blocks)
<pointfree> DSI = Digital System Interconnect (the topmost and lowermost rows of routing tiles above and below the UDB array responsible for connecting the UDB array with other peripherals such as portpins, digital filter blocks, and many other things)
<rqou> and where do the peripherals appear in the diagram on psoctools?
<pointfree> (the DSI routing blocks have identical structure to UDB routing blocks except that they are associated with other peripherals and not UDB's)
<rqou> wait, so why are there "DSI routing blocks" and "UDB routing blocks"
<pointfree> This here is an incomplete list of peripherals on the lower and upper dsi rows http://www.psoctools.org/mappings-between-peripherals-and-dsi.html
<pointfree> rqou: That's just how the registers are named in the TRM. I guess you could view the UDB's as being peripherals too, in a way.
<rqou> i thought you just said those were the PRT gpio ports?
<pointfree> I like to call portpins peripherals for the sake of simplicity.
<rqou> wait, so do _all_ physical pins go through the routing fabric?
<rqou> including analog?
<pointfree> You can route them through the DSI to other portpins or to a PLD or to something else.
<rqou> are the fixed peripherals the "???" connections
<rqou> ?
<pointfree> "???" means I don't know what's there yet.
<pointfree> placeholder
<rqou> so if the chip has a CAN or USB or whatever, where does it go?
<rqou> to a pinmux like a "normal" microcontroller or into this DSI routing?
<rqou> or both?
<pointfree> All of those are connected to the DSI and the PHUB, system bus, ARM Cortex-M3, etc.
<rqou> and then analog is completely separate?
<pointfree> for the most part, but you can route some of it to the DSI/UDB-array.
<rqou> and what is PHUB?
<pointfree> Peripheral Hub - it's a central backbone of the psoc with spokes connecting various systems on the PSoC, and it supports DMA.
<rqou> can you take all of this and draw a new block diagram? :P
<pointfree> an svg or something?
<rqou> wait, there's only hardwired CAN and USB?
<rqou> no hardwired e.g. UART?
<rqou> oh and I2C apparently?
<pointfree> that's it.
<rqou> so i'm reading the "PSoC® 5LP: CY8C58LP Family Datasheet"
<pointfree> everything else goes in the UDB array
<rqou> so under their "architecture overview" section
<rqou> "Digital Interconnect" is a combination of DSI/UDB routing?
<rqou> and "System Bus" is PHUB?
<pointfree> I just go by the register names. DSI7_HC, B0_P0_ROUTE_HC8, etc.
<rqou> but this means that someone like me who isn't paying attention too much won't have any idea what is happening
<rqou> pointfree: so on the block diagram on the front page
<rqou> those fat arrows themselves don't have any configuration, right?
<rqou> only the "HC" and "HV" blocks are configurable?
<pointfree> HC (horizontal channel), HV (horizontal-to-vertical), VS (vertical segmentation), HS (horizontal segmentation), PI (port interface) are all configurable and also very permutable.
<rqou> um, where do VS/HS show up?
<pointfree> they don't consume any coordinates but I put them in this diagram http://www.psoctools.org/switching-bits-and-regs.html
<rqou> yes, but what do they do? :P
<pointfree> you need them to drive left or right to another routing tile such as from DSI5 to DSI4
<pointfree> *or up/down
<rqou> isn't that what DSI4_HC does?
<pointfree> HC can connect things coming from HV, VS, or HS to a peripheral above or below HC through the PI (port interface). btw, you don't always need to use the HC.
<pointfree> ...to connect to a peripheral.
<rqou> so VS/HS/PI "surround" the HC stuff?
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<pointfree> PI is above HC (the biggest routing block). HS is between HV_L and and HV_R. VS is staggered above and below HV.
<pointfree> *PI is above or below HC
<rqou> can you please draw a new block diagram?
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<rqou> why does HV have a _L and _R?
<pointfree> to replace the ascii switching diagram?
<pointfree> HV left and right
<rqou> to replace udb-banks-and-routing.svg
<rqou> with all of the stuff you just explained
<pointfree> alright I'll be at it.
<rqou> because tbh i still don't fully understand
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<pointfree> rqou: I'm thinking I could put together a map combining udb-banks-and-routing.svg + switching-bit-and-regs.html into one searchable leaflet.js map. I haven't done that yet because I've prioritized RE and writing tools over aesthetically pleasing diagrams so far.
<rqou> hmm i guess i'm pretty guilty of that too
<rqou> my excuse is that the xilinx arch docs are really good
<rqou> :P
<pointfree> making pretty pictures is fun but it feels like bikeshedding.
<rqou> but it helps other people understand wtf is happening
<rqou> i actually have one for xc2, but it's non-free and can't really be shared
<pointfree> They are accessible from the DSI and the system bus. See where those UDB's are back to back with no HC inbetween? That's where the system bus is.
<rqou> btw azonenberg we need a private wiki for non-free diagrams or other data :P
<rqou> unless you want it on "fc:"
<azonenberg> that was the point ot fc, i think
<azonenberg> of*
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