<buhman>
https://ptpb.io/2W4VZ8.txt iverilog generates a waveform that I want with this, but yosys tells me there are driver conflicts for tx_ix, rx_ix, and miso. How do I fix this?
<buhman>
I understand why there are conflicts (due to the always blocks), but I'm uncertain of how else I could express the same waveform.
<tpw_rules>
you should only have clocks in always blocks
<tpw_rules>
like every single one should be always @(posedge clk) where clk is some master clock that's common to all your modules
<buhman>
sure. How does that work for SPI then? miso needs to transition to the first bit prior to the rising edge of the first clock.
<tpw_rules>
because that clock shouldn't be the spi clock
<buhman>
huh.
<buhman>
so I would sample CS on some other (internal) clock?
<tpw_rules>
yes
<tpw_rules>
that's how essentially all fpga designs (and synchronous digital logic chips) work
<buhman>
wouldn't that still conflict with sck though?
<tpw_rules>
well you would also sample sck
<buhman>
hmm, this sounds like a bit more logic than what I wrote
<tpw_rules>
yes it is
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<tnt>
So ... what's this fpga_interchange things I see lots of PRs about ?
<whitequark>
xilinx
<tnt>
Is it some sort of standard ? If it's just xilinx ... why not call it xilinx ?
<gatecat>
the idea is to apply to more families, e.g. quicklogic too
<gatecat>
but right now it's only xilinx (and it's a long way off being something end user ready)